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Nanomaterials

Wafer-Scale Electrical Characterization of Al/AlxOy/Al Tunnel Junctions for Process Monitoring at Room Temperature

Simon Lang, I. Eisele, Johannes Weber, Alexandra Schewski, Emir Music, Alwin Maiwald, Martin Hahn, Daniela Zahn, Zhen Luo, L. Nebrich, Benedikt Schoof, Thomas Mayer, Leonhard Sturm-Rogon, Wilfried Lerch, Rui N. Pereira, Christoph Kutter

Published May 7, 2026• 0 citations
Publisher

Abstract

Josephson junctions are key elements in superconducting qubits. Their efficient wafer-scale characterization is crucial for process control and optimization, motivating analysis approaches that extend beyond conventional cryogenic measurements. In this work, we demonstrate that room temperature (RT) capacitance and current–voltage measurements, combined with appropriate data analysis, enable extraction of relevant junction parameters such as oxide thickness, tunnel coefficient, and interfacial defect density. Furthermore, different charge transport mechanisms can be identified from detailed current–voltage analysis. We evaluate our characterization technique using tunnel junctions fabricated on 200 mm wafers in a complementary metal–oxide–semiconductor (CMOS)-compatible subtractive process. The results show a homogeneous average oxide thickness across the wafer with a variation below 3%. A dependence of the tunnel coefficient on oxide thickness indicates a stoichiometry gradient within the oxide. Additionally, low interfacial defect densities in the range of 70–5000 defects/cm2 are observed in our junctions, increasing with decreasing oxide thickness, suggesting that wet etching used for thickness control introduces interfacial trap states. Our study highlights the importance of advanced RT characterization for extracting tunnel junction parameters on the wafer scale, enabling effective process monitoring and optimization in industrial superconducting qubit manufacturing.

DOI
10.3390/nano16100569

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IEEE Transactions on Applied Superconductivity•Mar 30, 2026•0 citations
Josephson junctions are key elements in superconducting qubits. Their efficient wafer-scale characterization is crucial for process control and optimization, motivating analysis approaches that extend beyond conventional cryogenic measurements. In this work, we demonstrate that room temperature (RT) capacitance and current–voltage measurements, combined with appropriate data analysis, enable extraction of relevant junction parameters such as oxide thickness, tunnel coefficient, and interfacial defect density. Furthermore, different charge transport mechanisms can be identified from detailed current–voltage analysis. We evaluate our characterization technique using tunnel junctions fabricated on 200 mm wafers in a complementary metal–oxide–semiconductor (CMOS)-compatible subtractive process. The results show a homogeneous average oxide thickness across the wafer with a variation below 3%. A dependence of the tunnel coefficient on oxide thickness indicates a stoichiometry gradient within the oxide. Additionally, low interfacial defect densities in the range of 70–5000 defects/cm2 are observed in our junctions, increasing with decreasing oxide thickness, suggesting that wet etching used for thickness control introduces interfacial trap states. Our study highlights the importance of advanced RT characterization for extracting tunnel junction parameters on the wafer scale, enabling effective process monitoring and optimization in industrial superconducting qubit manufacturing.
Josephson tunnel junctions represent a key element in superconducting electronics and quantum circuits. For many years, shadow evaporation by means of Dolan-type bridges has been the state-of-the-art for deep sub- micrometer sized structures. Increasing demand in the number of Josephson junctions, e.g. in qubit circuits and travelling wave parametric amplifiers, requests for a wafer-scale fabrication process with precise control of junction parameters and have led to an advanced lift-off technique called Manhattan-type junction technology in recent years. Herein, we report on the development of a 100 mm wafer-scale fabrication technology for deep sub-micrometer sized Al Josephson junctions with linear dimensions down to 180 nm. The critical currentICof the junctions ranges from about 10 to 120 nA scaling with their linear dimensions. Low temperature transport measurements as well as room-temperature characterization has been used forICand process homogeneity determination of series arrays of up to 50 Josephson junctions. We discuss technology parameters such as yield, on-chip and on-wafer reproducibility of the junction's critical currents as well as main process limitations. Moreover, we present experimental results on the characterization of first transmon-type qubits fabricated using this technology.
This work focuses on the manufacturing of Al/AlOx/Al Josephson junctions (JJs), which are essential components of many quantum circuits. Two processes were studied to understand the oxidation of the aluminum surface. Static oxidation was performed by removing native AlOx in a cluster system with Ar-ion beam milling and controlling the final tunneling oxide by applying a specific O2 pressure in the chamber. Controlled plasma oxidation was performed by removing native AlOx with a H2 plasma followed by a defined reoxidation with an oxygen plasma. The resulting oxides had thicknesses up to 10 nm and their electrical properties were analyzed on wafer level, providing insight into the structure and composition of the aluminum oxides and their applicability for Qubits. This work is crucial for reliable industrial manufacturing on full-scale 200 mm wafers with a very high uniformity level.
Abstract Quantum bits, or qubits, are an example of coherent circuits envisioned for next-generation computers and detectors. A robust superconducting qubit with a coherent lifetime of O(100 µs) is the transmon: a Josephson junction functioning as a non-linear inductor shunted with a capacitor to form an anharmonic oscillator. In a complex device with many such transmons, precise control over each qubit frequency is often required, and thus variations of the junction area and tunnel barrier thickness must be sufficiently minimized to achieve optimal performance while avoiding spectral overlap between neighboring circuits. Simply transplanting our recipe optimized for single, stand-alone devices to wafer-scale (producing 64, 1x1 cm dies from a 150 mm wafer) initially resulted in global drifts in room-temperature tunneling resistance of ± 30%. Inferring a critical current I c variation from this resistance distribution, we present an optimized process developed from a systematic 38 wafer study that results in < 3.5% relative standard deviation (RSD) in critical current ( ≡ σ I c / I c ) for 3000 Josephson junctions (both single-junctions and asymmetric SQUIDs) across an area of 49 cm2. Looking within a 1x1 cm moving window across the substrate gives an estimate of the variation characteristic of a given qubit chip. Our best process, utilizing ultrasonically assisted development, uniform ashing, and dynamic oxidation has shown σ I c / I c = 1.8% within 1x1 cm, on average, with a few 1x1 cm areas having σ I c / I c < 1.0% (equivalent to σ f / f < 0.5%). Such stability would drastically improve the yield of multi-junction chips with strict critical current requirements.
Fabrication And Characterization Of High-Quality Nb/Al-AlOx_xx​/Nb Cross-Type Josephson Tunnel Junctions Utilising CMP-based Planarisation Techniques
Josephson tunnel junctions (JJs) are the fundamental building blocks of today's most advanced superconducting electronic components, such as qubits and superconducting quantum interference devices (SQUIDs). Given the ongoing demand for scalability of these devices on the wafer-scale, it is crucial to control the fabrication process as precisely as possible to ensure uniform quality and reproducibility. Today, window-type JJs are often used in the production of DC SQUIDs and while they are reliable and reproducible, they suffer from alignment inaccuracies caused by photolithography and unavoidable parasitic capacitances, thus limiting the energy sensitivity of DC SQUIDs. These problems can be circumvented by producing JJs with cross-type geometry, which allows for smaller junction areas and eliminates parasitic capacitances. Here we discuss the fabrication of Nb/Al-AlOx/Nb-based cross-type JJs, where the trilayer is embedded in sputter-deposited SiO2_22​ to allow for planarisation of the structures and to ensure the reliable insulation of the sidewalls of the bottom electrode. Instead of lift-off processes that require a lot of time and potentially leave unwanted wings along the edges of microstructures behind that might compromise subsequent layers, we use chemical-mechanical polishing (CMP) for the removal of excess SiO2_22​. This is not only much faster, but produces smooth and uniform surfaces, which in turn effectively improves the reliability of our JJ production process resulting in a high yield of over 90 %90\,\%90% on wafer-scale. In addition, we discuss the influence of fabrication details on the quality and electrical properties of our JJs with different junction areas down to 1 μm×1 μm1\,\mathrm{μm} \times 1\,\mathrm{μm}1μm×1μm distributed across the wafer and extract the junction specific quality parameters from their IV-characteristics and their Fraunhofer patterns.
Using a fully automated cryogenic wafer prober, we measured superconductor fabrication process control monitors and simple integrated circuits on 200 mm wafers at 4.2 K, including Nb/Al-AlOx/Nb Josephson junctions, SQUID-based circuits for measuring inductors, test structures for measuring critical current of superconducting wires and vias, resistors, etc., to demonstrate the feasibility of using the system for characterizing niobium superconducting devices and integrated circuits on a wafer scale. The data on the wafer-scale distributions of the junction tunnel resistance, energy gap, inductance of Nb layers, critical currents of interlayer vias are presented. The wafers were fabricated in the SFQ5ee process, the fully planarized process with eight niobium layers and a layer of kinetic inductors, developed for superconductor electronics at MIT Lincoln Laboratory. The cryogenic wafer prober was developed at HPD/ FormFactor, Inc.
We develop a fully complementary metal-oxide semiconductor (CMOS) fabrication technique for the realization of a superconducting qubit network (SQN). In our current research work, we focus on a single-angle overlap Josephson junction fabrication technique, based on the lift-off process for defining both base and top electrodes, avoiding the wiring insulator layer and requiring an RF Ar etching process before AlOxbarrier growth. The fabricated Al/AlOx/Al microscale Josephson junctions have been tested at low temperature (T = 300 mK) in the superconducting state using current–voltage characteristic measurements.