This work focuses on the manufacturing of Al/AlOx/Al Josephson junctions (JJs), which are essential components of many quantum circuits. Two processes were studied to understand the oxidation of the aluminum surface. Static oxidation was performed by removing native AlOx in a cluster system with Ar-ion beam milling and controlling the final tunneling oxide by applying a specific O2 pressure in the chamber. Controlled plasma oxidation was performed by removing native AlOx with a H2 plasma followed by a defined reoxidation with an oxygen plasma. The resulting oxides had thicknesses up to 10 nm and their electrical properties were analyzed on wafer level, providing insight into the structure and composition of the aluminum oxides and their applicability for Qubits. This work is crucial for reliable industrial manufacturing on full-scale 200 mm wafers with a very high uniformity level.
This work focuses on the manufacturing of Al/AlOx/Al Josephson junctions (JJs), which are essential components of many quantum circuits. Two processes were studied to understand the oxidation of the aluminum surface. Static oxidation was performed by removing native AlOx in a cluster system with Ar-ion beam milling and controlling the final tunneling oxide by applying a specific O2 pressure in the chamber. Controlled plasma oxidation was performed by removing native AlOx with a H2 plasma followed by a defined reoxidation with an oxygen plasma. The resulting oxides had thicknesses up to 10 nm and their electrical properties were analyzed on wafer level, providing insight into the structure and composition of the aluminum oxides and their applicability for Qubits. This work is crucial for reliable industrial manufacturing on full-scale 200 mm wafers with a very high uniformity level.
Fabrication And Characterization Of High-Quality Nb/Al-AlOx/Nb Cross-Type Josephson Tunnel Junctions Utilising CMP-based Planarisation Techniques
Josephson tunnel junctions (JJs) are the fundamental building blocks of today's most advanced superconducting electronic components, such as qubits and superconducting quantum interference devices (SQUIDs). Given the ongoing demand for scalability of these devices on the wafer-scale, it is crucial to control the fabrication process as precisely as possible to ensure uniform quality and reproducibility. Today, window-type JJs are often used in the production of DC SQUIDs and while they are reliable and reproducible, they suffer from alignment inaccuracies caused by photolithography and unavoidable parasitic capacitances, thus limiting the energy sensitivity of DC SQUIDs. These problems can be circumvented by producing JJs with cross-type geometry, which allows for smaller junction areas and eliminates parasitic capacitances. Here we discuss the fabrication of Nb/Al-AlOx/Nb-based cross-type JJs, where the trilayer is embedded in sputter-deposited SiO2 to allow for planarisation of the structures and to ensure the reliable insulation of the sidewalls of the bottom electrode. Instead of lift-off processes that require a lot of time and potentially leave unwanted wings along the edges of microstructures behind that might compromise subsequent layers, we use chemical-mechanical polishing (CMP) for the removal of excess SiO2. This is not only much faster, but produces smooth and uniform surfaces, which in turn effectively improves the reliability of our JJ production process resulting in a high yield of over 90% on wafer-scale. In addition, we discuss the influence of fabrication details on the quality and electrical properties of our JJs with different junction areas down to 1μm×1μm distributed across the wafer and extract the junction specific quality parameters from their IV-characteristics and their Fraunhofer patterns.
Reproducible Josephson junction (JJ) characteristics are essential for frequency-deterministic and scalable superconducting quantum processors. We show that the normal-state resistance and its reproducibility in Al/AlOx/Al JJs are governed not by oxide thickness, but by fabrication-history–induced disorder in the tunneling barrier. By comparing junctions fabricated on bare wafers, lift-off–processed base layers, and dry-etched base layers under identical oxidation conditions, we observe large differences in resistance and wafer-to-wafer variability. Atomic force microscopy reveals distinct surface disorder imprinted by prior fabrication steps, while cross-sectional transmission electron microscopy show that the average AlOx barrier thickness is comparable across the three fabrication histories within experimental uncertainty. The enhanced resistance on rough, plasma-damaged surfaces therefore originates from nanoscale barrier disorder rather than thickness variations. These results establish fabrication history as a key determinant of JJ barrier quality and highlight the need for holistic process control to achieve deterministic qubit frequency targeting.
Josephson junctions are key elements in superconducting qubits. Their efficient wafer-scale characterization is crucial for process control and optimization, motivating analysis approaches that extend beyond conventional cryogenic measurements. In this work, we demonstrate that room temperature (RT) capacitance and current–voltage measurements, combined with appropriate data analysis, enable extraction of relevant junction parameters such as oxide thickness, tunnel coefficient, and interfacial defect density. Furthermore, different charge transport mechanisms can be identified from detailed current–voltage analysis. We evaluate our characterization technique using tunnel junctions fabricated on 200 mm wafers in a complementary metal–oxide–semiconductor (CMOS)-compatible subtractive process. The results show a homogeneous average oxide thickness across the wafer with a variation below 3%. A dependence of the tunnel coefficient on oxide thickness indicates a stoichiometry gradient within the oxide. Additionally, low interfacial defect densities in the range of 70–5000 defects/cm2 are observed in our junctions, increasing with decreasing oxide thickness, suggesting that wet etching used for thickness control introduces interfacial trap states. Our study highlights the importance of advanced RT characterization for extracting tunnel junction parameters on the wafer scale, enabling effective process monitoring and optimization in industrial superconducting qubit manufacturing.
The aluminum oxide tunnel junction is a key component of the majority of superconducting quantum devices. For high-quality, reproducible, and scalably manufacturable qubits, the ability to fabricate Josephson junctions (JJs) with a targeted critical current and high uniformity is essential. We use first-principles modeling to assess fundamental aspects of the atomic structure of both amorphous and crystalline aluminum oxide tunnel junctions and relate the structure to predicted performance metrics. We use modified ab initio molecular dynamics to develop realistic models of the tunnel junction, from which interface roughness and local thickness fluctuations are analyzed in an unbiased manner by training a neural network to identify the boundary between metal and oxide. We show that the effective thickness of the insulating part of the junction can be different from the apparent physical thickness. We calculate the rate of Cooper pair tunneling for the atomically resolved electrostatic potential using direct numerical solution in 3D, which shows a channeling effect that impacts the junction critical current. The predicted critical current is a useful JJ design parameter that can be accessed from the ab initio calculations without fitting parameters. To assess the limits of uniformity and fabrication choices (e.g., oxidation vs epitaxy), we compare the amorphous junctions to crystalline models, which show order of magnitude more efficient tunneling compared to the amorphous case, underlining the connection between atomistic structure and Cooper pair tunneling efficiency. Further, this work provides a foundation for ab initio materials design and evaluation to help accelerate future development of improved tunnel junctions.
Superconducting qubits in today's quantum processing units are typically fabricated with angle-evaporated aluminum--aluminum-oxide--aluminum Josephson junctions. However, there is an urgent need to overcome the limited reproducibility of this approach when scaling up the number of qubits and junctions. Fabrication methods based on subtractive patterning of superconductor--insulator--superconductor trilayers, used for more classical large-scale Josephson junction circuits, could provide the solution but they in turn often suffer from lossy dielectrics incompatible with high qubit coherence. In this work, we utilize native aluminum oxide as a sidewall passivation layer for junctions based on aluminum--aluminum-oxide--niobium trilayers, and use such junctions in qubits. We design the fabrication process such that the few-nanometer-thin native oxide is not exposed to oxide removal steps that could increase its defect density or hinder its ability to prevent shorting between the leads of the junction. With these junctions, we design and fabricate transmon-like qubits and measure time-averaged coherence times up to 30 μs at a qubit frequency of 5 GHz, corresponding to a qubit quality factor of one million. Our process uses subtractive patterning and optical lithography on wafer scale, enabling high throughput in patterning. This approach provides a scalable path toward fabrication of superconducting qubits on industry-standard platforms.
Abstract Tantalum and aluminum on sapphire are widely used platforms for qubits of long coherent time. As quantum chips scale up, the number of Josephson junctions on Sapphire increases. Thus, both the uniformity and stability of the junctions are crucial to quantum devices, such as scalable superconducting quantum computer circuit, and quantum-limited amplifiers. By optimizing the fabrication process, especially, the conductive layer during the electron beam lithography process, Al/AlOx/Al junctions of sizes ranging from 0.0169 to 0.04 µm2 on sapphire substrates were prepared. The relative standard deviation of room temperature resistances (RN) of these junctions is better than 1.7% on 15 mm×15 mm chips, and better than 2.66% on 2 inch wafers, which is the highest uniformity on sapphire substrates has been reported. The junctions are robust and stable in resistances as temperature changes. The resistances increase by the ratio of 9.73% relative to RN as the temperature ramp down to 4K, and restore their initial values in the reverse process as the temperature ramps back to RT. After being stored in a nitrogen cabinet for 100 days, the resistance of the junctions changed by1.16% in average. The demonstration of uniform and stable Josephson junctions in large area paves the way for the fabrication of superconducting chip of hundreds of qubits on sapphire substrates.