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Scientific Reports

Impact of fabrication history induced disorder on Josephson junction reproducibility and qubit performance

Dae-Yun Kim, Hyeokshin Kwon, Dae Seok Han, Kiho Kim, Hyoung Kug Kim, ChungSun Lee, Geunyong Kim, June-Young M. Lee, Dongmin Kim, Eun-A Kim, Jaeho Shin

Published Apr 10, 2026• 0 citations
Publisher

Abstract

Reproducible Josephson junction (JJ) characteristics are essential for frequency-deterministic and scalable superconducting quantum processors. We show that the normal-state resistance and its reproducibility in Al/AlOx/Al JJs are governed not by oxide thickness, but by fabrication-history–induced disorder in the tunneling barrier. By comparing junctions fabricated on bare wafers, lift-off–processed base layers, and dry-etched base layers under identical oxidation conditions, we observe large differences in resistance and wafer-to-wafer variability. Atomic force microscopy reveals distinct surface disorder imprinted by prior fabrication steps, while cross-sectional transmission electron microscopy show that the average AlOx barrier thickness is comparable across the three fabrication histories within experimental uncertainty. The enhanced resistance on rough, plasma-damaged surfaces therefore originates from nanoscale barrier disorder rather than thickness variations. These results establish fabrication history as a key determinant of JJ barrier quality and highlight the need for holistic process control to achieve deterministic qubit frequency targeting.

DOI
10.1038/s41598-026-46352-w

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ECS Transactions•May 19, 2023•4 citations
Reproducible Josephson junction (JJ) characteristics are essential for frequency-deterministic and scalable superconducting quantum processors. We show that the normal-state resistance and its reproducibility in Al/AlOx/Al JJs are governed not by oxide thickness, but by fabrication-history–induced disorder in the tunneling barrier. By comparing junctions fabricated on bare wafers, lift-off–processed base layers, and dry-etched base layers under identical oxidation conditions, we observe large differences in resistance and wafer-to-wafer variability. Atomic force microscopy reveals distinct surface disorder imprinted by prior fabrication steps, while cross-sectional transmission electron microscopy show that the average AlOx barrier thickness is comparable across the three fabrication histories within experimental uncertainty. The enhanced resistance on rough, plasma-damaged surfaces therefore originates from nanoscale barrier disorder rather than thickness variations. These results establish fabrication history as a key determinant of JJ barrier quality and highlight the need for holistic process control to achieve deterministic qubit frequency targeting.
Abstract To maximize the yield of scalable superconducting quantum processors, we introduce a fabrication strategy that prioritizes the formation of Josephson junctions (JJs) before the shunting capacitors. The junction-first approach minimizes the impact of accumulated process-induced surface modifications on the JJ interface. We show through wafer-scale statistical measurements that this sequence substantially reduces fluctuations in junction resistance across different wafers. Surface analysis via transmission electron microscopy and atomic force microscopy identifies that preceding lithography and etching steps in conventional workflows damage the substrate surface, leading to non-uniform junction morphology. The compatibility of this process with high-performance qubit operation is demonstrated through the fabrication of an eight-qubit quantum processing unit. The resulting coherence times remain sufficient for fully functional qubit operation, confirming that that the junction-first process significantly enhances junction reproducibility while maintaining viable qubit performance, offering a scalable pathway for next-generation quantum hardware.
Josephson junctions (JJs) are critical components in superconducting quantum circuits, where their electrical properties directly determine qubit transition frequencies. While advances in fabrication have enabled precise control over junction area and oxide thickness, the influence of junction geometry beyond area has remained largely unexplored. Here, we report clear and reproducible evidence that the normal-state resistance (Rn) of JJs depends strongly on geometric parameters, demonstrating that (Rn) exhibits a systematic and reproducible dependence on junction geometry beyond simple area scaling. To account for this behavior, we introduce an edge-resistance model that incorporates perimeter-related contributions to (Rn). Our findings highlight the crucial role of geometric design in JJ electrical characteristics and provide a practical framework for improving frequency precision and uniformity in large-scale superconducting quantum processors.
Superconducting qubit fabrication innovations continue to be explored to achieve higher performance. Despite improvements to base layer fabrication and processing, resist-based Josephson junction (JJ) schemes have largely remained unchanged. The polymer mask during deposition causes chemical contamination and limits in situ and ex situ surface preparation, junction materials, and scalability. Here, we demonstrate a resist-free approach to junction fabrication based on etched silicon trenches that is CMOS compatible and easily integrated into existing innovations in qubit base layer fabrication and chemical processing. We fabricate Al-AlOx-Al JJs and qubits using this method, measuring median energy relaxation times up to 184 microseconds. We find minimal contamination at the substrate-metal interface and fluctuations of energy relaxation on a 35 hour timescale that are narrow and normally distributed. The method widens the process window for substrate preparation and new materials platforms.
One of the practical limitations of solid-state superconducting quantum processors is the collision of the qubit resonance frequencies, caused by their deviation from the design specifications due to the low reproducibility in qubit fabrication. Josephson junction 100 nm-scale nonlinear inductance of the qubits still suffers from Dolan-bridge shadow evaporation process. Here, we report on a robust wafer-scale Al/AlOx/Al Dolan-bridge Josephson junction (JJ) process using preliminary shadow evaporation bias resist mask correction and comprehensive oxidation optimization. We introduce a topology correction model for two-layer resist mask biasing at a wafer-scale, which takes into account an evaporation source geometry. It results in Josephson junction area variation coefficient (  CVA\:{CV}_{A}CVA​ ) improvement down to 1.1% for the critical dimensions from 130 × 170 nm2 to 130 × 670 nm2 over 70 × 70 mm2 (49 cm2) wafer working area. Next, we investigate JJ oxidation process (oxidation method, pressure and time) and its impact on the room temperature resistance reproducibility. Finally, we combine both shadow evaporation bias correction and oxidation best practices for 4-inch wafers, improving  CVRN\:{CV}_{{R}_{N}}CVRN​​ down to 6.0/5.2/4.1% for 0.025 µm2 JJ area and 4.0/3.4/2.3% for 0.090 µm2 JJ area for 49/25/16 cm2 wafer working area correspondingly. The proposed model and oxidation method can be useful for robust wafer-scale superconducting quantum processors fabrication.
Fabrication And Characterization Of High-Quality Nb/Al-AlOx_xx​/Nb Cross-Type Josephson Tunnel Junctions Utilising CMP-based Planarisation Techniques
Josephson tunnel junctions (JJs) are the fundamental building blocks of today's most advanced superconducting electronic components, such as qubits and superconducting quantum interference devices (SQUIDs). Given the ongoing demand for scalability of these devices on the wafer-scale, it is crucial to control the fabrication process as precisely as possible to ensure uniform quality and reproducibility. Today, window-type JJs are often used in the production of DC SQUIDs and while they are reliable and reproducible, they suffer from alignment inaccuracies caused by photolithography and unavoidable parasitic capacitances, thus limiting the energy sensitivity of DC SQUIDs. These problems can be circumvented by producing JJs with cross-type geometry, which allows for smaller junction areas and eliminates parasitic capacitances. Here we discuss the fabrication of Nb/Al-AlOx/Nb-based cross-type JJs, where the trilayer is embedded in sputter-deposited SiO2_22​ to allow for planarisation of the structures and to ensure the reliable insulation of the sidewalls of the bottom electrode. Instead of lift-off processes that require a lot of time and potentially leave unwanted wings along the edges of microstructures behind that might compromise subsequent layers, we use chemical-mechanical polishing (CMP) for the removal of excess SiO2_22​. This is not only much faster, but produces smooth and uniform surfaces, which in turn effectively improves the reliability of our JJ production process resulting in a high yield of over 90 %90\,\%90% on wafer-scale. In addition, we discuss the influence of fabrication details on the quality and electrical properties of our JJs with different junction areas down to 1 μm×1 μm1\,\mathrm{μm} \times 1\,\mathrm{μm}1μm×1μm distributed across the wafer and extract the junction specific quality parameters from their IV-characteristics and their Fraunhofer patterns.
This work focuses on the manufacturing of Al/AlOx/Al Josephson junctions (JJs), which are essential components of many quantum circuits. Two processes were studied to understand the oxidation of the aluminum surface. Static oxidation was performed by removing native AlOx in a cluster system with Ar-ion beam milling and controlling the final tunneling oxide by applying a specific O2 pressure in the chamber. Controlled plasma oxidation was performed by removing native AlOx with a H2 plasma followed by a defined reoxidation with an oxygen plasma. The resulting oxides had thicknesses up to 10 nm and their electrical properties were analyzed on wafer level, providing insight into the structure and composition of the aluminum oxides and their applicability for Qubits. This work is crucial for reliable industrial manufacturing on full-scale 200 mm wafers with a very high uniformity level.