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arXiv:2604.09796 · Nano Letters

Resist-free shadow deposition using silicon trenches for Josephson junctions in superconducting qubits

Tathagata Banerjee, Stephen Daniel Funni, Saswata Roy, Judy J. Cha, Valla Fatemi

quant-phphysics.app-phSubmitted Apr 10, 2026• Announced Apr 14, 2026• 0 citations• Revised May 15, 2026 (v2)
v1 · Apr 10, 2026v2 · May 15, 2026
arXivHTMLPDF

Abstract

Superconducting qubit fabrication innovations continue to be explored to achieve higher performance. Despite improvements to base layer fabrication and processing, resist-based Josephson junction (JJ) schemes have largely remained unchanged. The polymer mask during deposition causes chemical contamination and limits in situ and ex situ surface preparation, junction materials, and scalability. Here, we demonstrate a resist-free approach to junction fabrication based on etched silicon trenches that is CMOS compatible and easily integrated into existing innovations in qubit base layer fabrication and chemical processing. We fabricate Al-AlOx-Al JJs and qubits using this method, measuring median energy relaxation times up to 184 microseconds. We find minimal contamination at the substrate-metal interface and fluctuations of energy relaxation on a 35 hour timescale that are narrow and normally distributed. The method widens the process window for substrate preparation and new materials platforms.

Journal reference
Nano Letters (2026)
DOI
10.1021/acs.nanolett.6c02734
Comments
7 pages, 5 figures, supplementary material (8 pages, 9 figures, 2 tables); minor corrections, added/updated references, added discussion and further calculations in Appendix

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Superconducting qubit fabrication innovations continue to be explored to achieve higher performance. Despite improvements to base layer fabrication and processing, resist-based Josephson junction (JJ) schemes have largely remained unchanged. The polymer mask during deposition causes chemical contamination and limits in situ and ex situ surface preparation, junction materials, and scalability. Here, we demonstrate a resist-free approach to junction fabrication based on etched silicon trenches that is CMOS compatible and easily integrated into existing innovations in qubit base layer fabrication and chemical processing. We fabricate Al-AlOx-Al JJs and qubits using this method, measuring median energy relaxation times up to 184 microseconds. We find minimal contamination at the substrate-metal interface and fluctuations of energy relaxation on a 35 hour timescale that are narrow and normally distributed. The method widens the process window for substrate preparation and new materials platforms.
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The authors have developed two distinct processes for the fabrication of mesoscopic Josephson junction qubits that are compatible with conventional CMOS processing. These devices, based on superconducting Al/Al2O3/Al tunnel junctions, are fabricated by electron beam lithography using single-layer and multi-layer resists. The new single-layer resist process is found to have significant advantages over conventional fabrication methods using suspended tri-layer shadow masks. It is simpler and more accurate to implement, and avoids the significant areas of redundant metallisation that are an unavoidable by-product of the tri-layer shadow mask method.
We report on the fabrication of Josephson junction and superconducting bridges using a damascene CMP process applied for a first time to superconductors. The demonstrated industrial reliability of damascene CMP processes on large scale semiconductor circuits is a major incentive for our research that should allow large numbers of nanometric Josephson junctions to be fabricated in both Nb and Al, the two main material employed in superconducting quantum computing (qubit) and RSFQ electronics fabrication.We carried out a Chemical-Mechanical Polishing (CMP) process on Nb and Al films deposited on a SiO2 layer patterned with trenches of 100 to 300 nm of nominal depth. The process formed long bridges, 1 to 4 μm wide. The susceptibility and resistive transitions showed that CMP has no observable influence on superconductivity.We have also developed a hybrid technique that uses Al/Al2O3/Al shadow evaporation in the trenches before the damascene CMP process. This allows for high quality “in-situ” junction oxidation with the size reduction benefit provided by the damascene CMP process. We easily reach junctions sizes near 0.5 μm2 which are difficult to fabricate by other methods.We describe these techniques and report on measurements on large bridges and junctions and on the fabrication and measurements of Al and Nb nanobridges.
The present thesis focuses on the laboratory fabrication of Al/AlOₓ/Al Josephson junctions using a bridge-free shadow evaporation technique, developed within the broader context of superconducting technologies for quantum computing. The interest in such devices arises from the central role played by the Josephson junction in superconducting qubits: unlike a purely harmonic LC oscillator, characterized by equally spaced energy levels, the presence of the junction introduces a nonlinearity that leads to an anharmonic energy spectrum. This allows for the selective addressing of the fundamental transition, which is a necessary condition for implementing a circuit-based qubit. In this framework, the quality of the AlOₓ tunnel barrier and of the metal interfaces is of crucial importance, as it directly affects not only the static electrical parameters of the junction but also dielectric losses and, more generally, the performance of the device in quantum applications. Following a theoretical overview of superconducting qubits and the physics of Al/AlOₓ/Al Josephson junctions, the work focuses on the experimental implementation and optimization of a bridge-free fabrication approach, adopted as an alternative to conventional suspended-bridge techniques. This method preserves the advantages of in-situ shadow evaporation for barrier formation while replacing the mechanical fragility of the suspended bridge with a geometrical control of the resist undercut. The operating principle relies on engineering an asymmetric profile in a bilayer resist system such that, during the two angled evaporations, only one deposition reaches the substrate along the connection lines, while the other is deposited on the resist sidewalls and subsequently removed during lift-off. In the central region, the overlap of the two evaporated aluminum layers, separated by an intermediate oxidation step, defines the Al/AlOₓ/Al superconductor–insulator–superconductor structure. This approach results in a more robust masking scheme compared to suspended-bridge processes, albeit at the cost of increased sensitivity to the precise definition and reproducibility of the undercut. The experimental activity was structured in several stages. First, the positive resists PMMA and MMA, used to form the bilayer lithographic stack, were characterized in order to determine their response as a function of electron-beam exposure dose and development conditions. A calibration mask consisting of an array of square patterns exposed at varying doses was employed to extract contrast curves and identify suitable exposure parameters. The development depth was quantitatively measured using atomic force microscopy (AFM), enabling a direct correlation between exposure dose and resulting resist profile. This step proved essential for selecting the most appropriate resist configuration capable of producing a controlled undercut compatible with the requirements of the bridge-free process. Subsequently, the lithographic process and evaporation geometry were calibrated through iterative refinement of the mask design, exposure parameters, and development conditions. Cross-sectional analysis, obtained via controlled sample cleaving followed by scanning electron microscopy (SEM), played a key role in assessing the three-dimensional profile of the resist, verifying the presence and quality of the undercut, and identifying potential structural instabilities such as resist collapse. At the same time, modifications were introduced to the evaporation system to enable deposition at the desired angles. This required the design of a new sample holder and a complete recalibration of the quartz crystal microbalance, as the altered geometry significantly affected the relationship between the nominal thickness reading and the actual film thickness deposited on the sample. A further important aspect of the work involved the progressive design and optimization of the full device mask, including contact pads, alignment markers, and the active junction region. The evolution of the layout, from initial test structures to the final configuration, was guided by experimental observations of pattern distortions and dose non-uniformities. It was found that the writing order of the electron-beam lithography pattern generator could significantly influence the final pattern quality, introducing systematic variations in feature definition. To mitigate this effect, a constrained writing sequence was implemented, ensuring improved reproducibility of the exposure process. Once all process parameters were stabilized, a comprehensive Standard Operating Procedure (SOP) was established, covering both the fabrication of Cr/Au contact structures and the subsequent lithography, angled evaporation, oxidation, and lift-off steps required for the realization of the Josephson junction. Finally, prior to fabricating fully oxidized junctions, a preliminary electrical validation of the process was carried out by producing test structures without the intermediate oxidation step. This allowed for the verification of electrical continuity in the aluminum structures. Measurements performed using a probe station confirmed ohmic behavior and the absence of macroscopic discontinuities in the conduction path. The measured resistance values were higher than those predicted using bulk aluminum resistivity; however, this discrepancy is consistent with the well-known behavior of thin evaporated films, in which surface scattering, grain boundaries, and interface effects lead to an increased effective resistivity. Although these measurements do not yet constitute a full characterization of the Josephson junction in the quantum regime, they provide an essential validation of the fabrication process and the structural integrity of the devices. In conclusion, this work enabled the development and calibration of a bridge-free fabrication process for Al/AlOₓ/Al Josephson junctions, highlighting the strong interplay between lithographic control, evaporation geometry, barrier formation, and electrical response. The main contribution of the thesis lies in transforming a conceptual fabrication approach into a structured and reproducible experimental procedure, based on resist characterization, cross-sectional analysis, instrumental recalibration, and preliminary electrical validation. The results obtained provide a solid foundation for further optimization of the tunnel barrier, cryogenic characterization, and integration of these junctions into superconducting circuits for quantum computing applications.
Reproducible Josephson junction (JJ) characteristics are essential for frequency-deterministic and scalable superconducting quantum processors. We show that the normal-state resistance and its reproducibility in Al/AlOx/Al JJs are governed not by oxide thickness, but by fabrication-history–induced disorder in the tunneling barrier. By comparing junctions fabricated on bare wafers, lift-off–processed base layers, and dry-etched base layers under identical oxidation conditions, we observe large differences in resistance and wafer-to-wafer variability. Atomic force microscopy reveals distinct surface disorder imprinted by prior fabrication steps, while cross-sectional transmission electron microscopy show that the average AlOx barrier thickness is comparable across the three fabrication histories within experimental uncertainty. The enhanced resistance on rough, plasma-damaged surfaces therefore originates from nanoscale barrier disorder rather than thickness variations. These results establish fabrication history as a key determinant of JJ barrier quality and highlight the need for holistic process control to achieve deterministic qubit frequency targeting.
The superconducting qubit is one of the promising directions in realizing fault-tolerant quantum computing (FTQC), which requires many high-quality qubits. To achieve this, it is desirable to leverage modern semiconductor industry technology to ensure quality, uniformity, and reproducibility. However, conventional Josephson junction fabrication relies mainly on resist-assisted double-angle evaporation, posing integration challenges. Here, we demonstrate a lift-off-free qubit fabrication that integrates seamlessly with existing industrial technologies. This method employs a silicon oxide (SiO 2 ) scaffold to define an etched window with a well-controlled size to form a Josephson junction. The SiO 2 , which has a large dielectric loss, is etched away in the final step using vapor HF, leaving little residue. This Window junction (WJ) process mitigates the degradation of qubit quality during fabrication and allows clean removal of the scaffold. The WJ process is validated by inspection and Josephson junction measurement. The scaffold removal process is verified by measuring the quality factor of the resonators. Furthermore, compared to scaffolds fabricated by plasma-enhanced chemical vapor deposition (PECVD), qubits made by WJ through physical vapor deposition (PVD) achieve relaxation time up to 57 μs. Our results pave the way for a lift-off-free qubit fabrication process, designed to be compatible with modern foundry tools and capable of minimizing damage to the substrate and material surfaces.