We report on the fabrication of Josephson junction and superconducting bridges using a damascene CMP process applied for a first time to superconductors. The demonstrated industrial reliability of damascene CMP processes on large scale semiconductor circuits is a major incentive for our research that should allow large numbers of nanometric Josephson junctions to be fabricated in both Nb and Al, the two main material employed in superconducting quantum computing (qubit) and RSFQ electronics fabrication.We carried out a Chemical-Mechanical Polishing (CMP) process on Nb and Al films deposited on a SiO2 layer patterned with trenches of 100 to 300 nm of nominal depth. The process formed long bridges, 1 to 4 μm wide. The susceptibility and resistive transitions showed that CMP has no observable influence on superconductivity.We have also developed a hybrid technique that uses Al/Al2O3/Al shadow evaporation in the trenches before the damascene CMP process. This allows for high quality “in-situ” junction oxidation with the size reduction benefit provided by the damascene CMP process. We easily reach junctions sizes near 0.5 μm2 which are difficult to fabricate by other methods.We describe these techniques and report on measurements on large bridges and junctions and on the fabrication and measurements of Al and Nb nanobridges.
We report on the fabrication of Josephson junction and superconducting bridges using a damascene CMP process applied for a first time to superconductors. The demonstrated industrial reliability of damascene CMP processes on large scale semiconductor circuits is a major incentive for our research that should allow large numbers of nanometric Josephson junctions to be fabricated in both Nb and Al, the two main material employed in superconducting quantum computing (qubit) and RSFQ electronics fabrication.We carried out a Chemical-Mechanical Polishing (CMP) process on Nb and Al films deposited on a SiO2 layer patterned with trenches of 100 to 300 nm of nominal depth. The process formed long bridges, 1 to 4 μm wide. The susceptibility and resistive transitions showed that CMP has no observable influence on superconductivity.We have also developed a hybrid technique that uses Al/Al2O3/Al shadow evaporation in the trenches before the damascene CMP process. This allows for high quality “in-situ” junction oxidation with the size reduction benefit provided by the damascene CMP process. We easily reach junctions sizes near 0.5 μm2 which are difficult to fabricate by other methods.We describe these techniques and report on measurements on large bridges and junctions and on the fabrication and measurements of Al and Nb nanobridges.
Fabrication And Characterization Of High-Quality Nb/Al-AlOx/Nb Cross-Type Josephson Tunnel Junctions Utilising CMP-based Planarisation Techniques
Josephson tunnel junctions (JJs) are the fundamental building blocks of today's most advanced superconducting electronic components, such as qubits and superconducting quantum interference devices (SQUIDs). Given the ongoing demand for scalability of these devices on the wafer-scale, it is crucial to control the fabrication process as precisely as possible to ensure uniform quality and reproducibility. Today, window-type JJs are often used in the production of DC SQUIDs and while they are reliable and reproducible, they suffer from alignment inaccuracies caused by photolithography and unavoidable parasitic capacitances, thus limiting the energy sensitivity of DC SQUIDs. These problems can be circumvented by producing JJs with cross-type geometry, which allows for smaller junction areas and eliminates parasitic capacitances. Here we discuss the fabrication of Nb/Al-AlOx/Nb-based cross-type JJs, where the trilayer is embedded in sputter-deposited SiO2 to allow for planarisation of the structures and to ensure the reliable insulation of the sidewalls of the bottom electrode. Instead of lift-off processes that require a lot of time and potentially leave unwanted wings along the edges of microstructures behind that might compromise subsequent layers, we use chemical-mechanical polishing (CMP) for the removal of excess SiO2. This is not only much faster, but produces smooth and uniform surfaces, which in turn effectively improves the reliability of our JJ production process resulting in a high yield of over 90% on wafer-scale. In addition, we discuss the influence of fabrication details on the quality and electrical properties of our JJs with different junction areas down to 1μm×1μm distributed across the wafer and extract the junction specific quality parameters from their IV-characteristics and their Fraunhofer patterns.
Superconducting qubit fabrication innovations continue to be explored to achieve higher performance. Despite improvements to base layer fabrication and processing, resist-based Josephson junction (JJ) schemes have largely remained unchanged. The polymer mask during deposition causes chemical contamination and limits in situ and ex situ surface preparation, junction materials, and scalability. Here, we demonstrate a resist-free approach to junction fabrication based on etched silicon trenches that is CMOS compatible and easily integrated into existing innovations in qubit base layer fabrication and chemical processing. We fabricate Al-AlOx-Al JJs and qubits using this method, measuring median energy relaxation times up to 184 microseconds. We find minimal contamination at the substrate-metal interface and fluctuations of energy relaxation on a 35 hour timescale that are narrow and normally distributed. The method widens the process window for substrate preparation and new materials platforms.
The present thesis focuses on the laboratory fabrication of Al/AlOₓ/Al Josephson junctions using a bridge-free shadow evaporation technique, developed within the broader context of superconducting technologies for quantum computing. The interest in such devices arises from the central role played by the Josephson junction in superconducting qubits: unlike a purely harmonic LC oscillator, characterized by equally spaced energy levels, the presence of the junction introduces a nonlinearity that leads to an anharmonic energy spectrum. This allows for the selective addressing of the fundamental transition, which is a necessary condition for implementing a circuit-based qubit. In this framework, the quality of the AlOₓ tunnel barrier and of the metal interfaces is of crucial importance, as it directly affects not only the static electrical parameters of the junction but also dielectric losses and, more generally, the performance of the device in quantum applications. Following a theoretical overview of superconducting qubits and the physics of Al/AlOₓ/Al Josephson junctions, the work focuses on the experimental implementation and optimization of a bridge-free fabrication approach, adopted as an alternative to conventional suspended-bridge techniques. This method preserves the advantages of in-situ shadow evaporation for barrier formation while replacing the mechanical fragility of the suspended bridge with a geometrical control of the resist undercut. The operating principle relies on engineering an asymmetric profile in a bilayer resist system such that, during the two angled evaporations, only one deposition reaches the substrate along the connection lines, while the other is deposited on the resist sidewalls and subsequently removed during lift-off. In the central region, the overlap of the two evaporated aluminum layers, separated by an intermediate oxidation step, defines the Al/AlOₓ/Al superconductor–insulator–superconductor structure. This approach results in a more robust masking scheme compared to suspended-bridge processes, albeit at the cost of increased sensitivity to the precise definition and reproducibility of the undercut. The experimental activity was structured in several stages. First, the positive resists PMMA and MMA, used to form the bilayer lithographic stack, were characterized in order to determine their response as a function of electron-beam exposure dose and development conditions. A calibration mask consisting of an array of square patterns exposed at varying doses was employed to extract contrast curves and identify suitable exposure parameters. The development depth was quantitatively measured using atomic force microscopy (AFM), enabling a direct correlation between exposure dose and resulting resist profile. This step proved essential for selecting the most appropriate resist configuration capable of producing a controlled undercut compatible with the requirements of the bridge-free process. Subsequently, the lithographic process and evaporation geometry were calibrated through iterative refinement of the mask design, exposure parameters, and development conditions. Cross-sectional analysis, obtained via controlled sample cleaving followed by scanning electron microscopy (SEM), played a key role in assessing the three-dimensional profile of the resist, verifying the presence and quality of the undercut, and identifying potential structural instabilities such as resist collapse. At the same time, modifications were introduced to the evaporation system to enable deposition at the desired angles. This required the design of a new sample holder and a complete recalibration of the quartz crystal microbalance, as the altered geometry significantly affected the relationship between the nominal thickness reading and the actual film thickness deposited on the sample. A further important aspect of the work involved the progressive design and optimization of the full device mask, including contact pads, alignment markers, and the active junction region. The evolution of the layout, from initial test structures to the final configuration, was guided by experimental observations of pattern distortions and dose non-uniformities. It was found that the writing order of the electron-beam lithography pattern generator could significantly influence the final pattern quality, introducing systematic variations in feature definition. To mitigate this effect, a constrained writing sequence was implemented, ensuring improved reproducibility of the exposure process. Once all process parameters were stabilized, a comprehensive Standard Operating Procedure (SOP) was established, covering both the fabrication of Cr/Au contact structures and the subsequent lithography, angled evaporation, oxidation, and lift-off steps required for the realization of the Josephson junction. Finally, prior to fabricating fully oxidized junctions, a preliminary electrical validation of the process was carried out by producing test structures without the intermediate oxidation step. This allowed for the verification of electrical continuity in the aluminum structures. Measurements performed using a probe station confirmed ohmic behavior and the absence of macroscopic discontinuities in the conduction path. The measured resistance values were higher than those predicted using bulk aluminum resistivity; however, this discrepancy is consistent with the well-known behavior of thin evaporated films, in which surface scattering, grain boundaries, and interface effects lead to an increased effective resistivity. Although these measurements do not yet constitute a full characterization of the Josephson junction in the quantum regime, they provide an essential validation of the fabrication process and the structural integrity of the devices. In conclusion, this work enabled the development and calibration of a bridge-free fabrication process for Al/AlOₓ/Al Josephson junctions, highlighting the strong interplay between lithographic control, evaporation geometry, barrier formation, and electrical response. The main contribution of the thesis lies in transforming a conceptual fabrication approach into a structured and reproducible experimental procedure, based on resist characterization, cross-sectional analysis, instrumental recalibration, and preliminary electrical validation. The results obtained provide a solid foundation for further optimization of the tunnel barrier, cryogenic characterization, and integration of these junctions into superconducting circuits for quantum computing applications.
Besides serving as promising candidates for realizing quantum computing, superconducting quantum circuits are one of a few macroscopic physical systems in which fundamental quantum phenomena can be directly demonstrated and tested, giving rise to a vast field of intensive research work both theoretically and experimentally. In this paper we report our work on the fabrication of superconducting quantum circuits, starting from its building blocks: Al/AlO x /Al Josephson junctions. By using electron beam lithography patterning and shadow evaporation, we have fabricated aluminum Josephson junctions with a controllable critical current density ( j c ) and wide range of junction sizes from 0.01 μm 2 up to 1 μm 2 . We have carried out systematical studies on the oxidation process in fabricating Al/AlO x /Al Josephson junctions suitable for superconducting flux qubits. Furthermore, we have also fabricated superconducting quantum circuits such as superconducting flux qubits and charge-flux qubits.
Josephson tunnel junctions are the centerpiece of almost any superconducting electronic circuit, including qubits. Typically, the junctions for qubits are fabricated using shadow evaporation techniques to reduce dielectric loss contributions from the superconducting film interfaces. In recent years, however, sub-micrometer scale overlap junctions have started to attract attention. Compared to shadow mask techniques, neither an angle dependent deposition nor free-standing bridges or overlaps are needed, which are significant limitations for wafer-scale processing. This comes at the cost of breaking the vacuum during fabrication, but simplifies integration in multi-layered circuits and implementation of vastly different junction sizes and enables fabrication on a larger scale in an industrially standardized process. In this work, we demonstrate the feasibility of a subtractive process for the fabrication of overlap junctions. In an array of test contacts, we find low aging of the average normal state resistance of only 1.6% over 6 months. We evaluate the coherence properties of the junctions by employing them in superconducting transmon qubits. In time domain experiments, we find that both, the qubit life- and coherence time of our best device, are, on average, greater than 20 μs. Finally, we discuss potential improvements to our technique. This work paves the way toward a more standardized process flow with advanced materials and growth processes, and constitutes an important step for the large scale fabrication of superconducting quantum circuits.
Development of 15kA/cm2 Fabrication Process for Superconducting Integrated Digital Circuits
A new fabrication process for superconducting integrated digital circuits is reported. We have developed the "SIMIT Nb04" fabrication technique for superconducting integrated circuits with Nb-based Josephson junctions based on the validated "SIMIT Nb03" process and Chemical Mechanical Planarization (CMP) technology. Seven Nb superconducting layers and one Mo resistor layer are included in the "SIMIT Nb04" process with 19 mask levels. The device structure is composed of active layers including junctions at the bottom, two passive transmission line (PTL) layers in the middle and a DC power layer at the top. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance Rsh of 3 Ω, followed by the deposition of Nb/Al-AlOx/Nb trilayer Josephson-junction with a target critical current density Jc at 15 kA/cm2. To increase the Al-AlOx barrier layer etching's repeatability, an additional barrier protection layer was applied. To accomplish high-quality planarization, we created a planarization procedure coupled with dummy filling. To assess the process dependability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and monitored. The successful manufacturing and testing of a few small-scale circuits, like our standard library cells, further attests to the viability of our fabrication process for superconducting integrated circuits.