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IEEE Transactions on Applied Superconductivity

Fabrication of Superconducting Qubits with Al Trilayer Josephson Junctions

T. Satoh, Yoshiji Noguchi, M. Yamagishi, Shuichi Nagasawa, K. Hinode, Mutsuo Hidaka, Masaaki Maezawa, Tsuyoshi Horikawa

Published Jan 1, 2014• 10 citations
Publisher

Abstract

To implement a large-scale integration of superconducting quantum bits (qubits), we have investigated a process of fabricating submicrometer Al/AlOx/Al trilayer Josephson junctions. Moreover, on the basis of this process, we developed a means of fabricating different kinds of superconducting qubits. Superconducting qubits require not only small junctions, but also peripheral circuit elements, such as a large resonator, on the same chip. As a result, we chose to use planarization in the self-aligned junction contact formation, which suppressed a pattern-area-dependence of the chemical-mechanical polishing rate. In addition, Al fine wires with a width of 0.2 μm were required in some parts of the qubits to increase the coupling strength between the SQUIDs and qubits. We developed a two-step etching process to form such fine wires using i-line photoresist, which had a high etching resistance. The operation of three-junction flux qubits was confirmed in a dilution refrigerator.

DOI
10.1109/tasc.2014.2378033

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To implement a large-scale integration of superconducting quantum bits (qubits), we have investigated a process of fabricating submicrometer Al/AlOx/Al trilayer Josephson junctions. Moreover, on the basis of this process, we developed a means of fabricating different kinds of superconducting qubits. Superconducting qubits require not only small junctions, but also peripheral circuit elements, such as a large resonator, on the same chip. As a result, we chose to use planarization in the self-aligned junction contact formation, which suppressed a pattern-area-dependence of the chemical-mechanical polishing rate. In addition, Al fine wires with a width of 0.2 μm were required in some parts of the qubits to increase the coupling strength between the SQUIDs and qubits. We developed a two-step etching process to form such fine wires using i-line photoresist, which had a high etching resistance. The operation of three-junction flux qubits was confirmed in a dilution refrigerator.
The performance of superconducting electronic devices such as superconducting quantum bits (qubits) and superconducting quantum interference devices (SQUIDs) strongly relies on high-quality Josephson junctions (JJ) and their integration into surrounding circuit elements. Therefore, a corresponding fabrication technology should allow for the fabrication of all required elements including the JJs, inductances, capacitances and waveguides. For a long time, shadow evaporation technique was the state of the art for the implementation of sub-μ m sized JJs based on aluminum for qubits of high coherence times. Although, the use of a single lithographic step represents a major advantage of this technique. However, shadowing effects limit sample size, device complexity, and thus scalability of the circuitry. To overcome these limitations and to meet the demands of next generation scalable quantum circuits, in this work we introduce our cross -type JJ aluminum technology, where JJs are defined by the overlap of two narrow perpendicular stripes. We discuss the technological challenges, with a focus on our newly developed dry etching process for patterning of the aluminum thin film. Compared to a lift-off based process, this advanced wafer-scale fabrication technology offers a high integration density and the required design flexibility. We will present first results on cross -type aluminum JJs.
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T1 relaxation times averaging above 50 μs (Q>1.5×106). Current shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. This eliminates a key bottleneck in manufacturing superconducting qubits by reducing the fabrication time and cost. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty 0.5×0.5-cm2 chips, with junction areas ranging between 0.01 and 0.16 μm2. The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4% and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7%–2.5%. We show that 60%–70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.
Superconducting qubits in today's quantum processing units are typically fabricated with angle-evaporated aluminum--aluminum-oxide--aluminum Josephson junctions. However, there is an urgent need to overcome the limited reproducibility of this approach when scaling up the number of qubits and junctions. Fabrication methods based on subtractive patterning of superconductor--insulator--superconductor trilayers, used for more classical large-scale Josephson junction circuits, could provide the solution but they in turn often suffer from lossy dielectrics incompatible with high qubit coherence. In this work, we utilize native aluminum oxide as a sidewall passivation layer for junctions based on aluminum--aluminum-oxide--niobium trilayers, and use such junctions in qubits. We design the fabrication process such that the few-nanometer-thin native oxide is not exposed to oxide removal steps that could increase its defect density or hinder its ability to prevent shorting between the leads of the junction. With these junctions, we design and fabricate transmon-like qubits and measure time-averaged coherence times up to 30 μμμs at a qubit frequency of 5 GHz, corresponding to a qubit quality factor of one million. Our process uses subtractive patterning and optical lithography on wafer scale, enabling high throughput in patterning. This approach provides a scalable path toward fabrication of superconducting qubits on industry-standard platforms.
Development of 15kA/cm2^22 Fabrication Process for Superconducting Integrated Digital Circuits
A new fabrication process for superconducting integrated digital circuits is reported. We have developed the "SIMIT Nb04" fabrication technique for superconducting integrated circuits with Nb-based Josephson junctions based on the validated "SIMIT Nb03" process and Chemical Mechanical Planarization (CMP) technology. Seven Nb superconducting layers and one Mo resistor layer are included in the "SIMIT Nb04" process with 19 mask levels. The device structure is composed of active layers including junctions at the bottom, two passive transmission line (PTL) layers in the middle and a DC power layer at the top. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance Rsh of 3 ΩΩΩ, followed by the deposition of Nb/Al-AlOx_xx​/Nb trilayer Josephson-junction with a target critical current density Jc at 15 kA/cm2^22. To increase the Al-AlOx_xx​ barrier layer etching's repeatability, an additional barrier protection layer was applied. To accomplish high-quality planarization, we created a planarization procedure coupled with dummy filling. To assess the process dependability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and monitored. The successful manufacturing and testing of a few small-scale circuits, like our standard library cells, further attests to the viability of our fabrication process for superconducting integrated circuits.
Superconducting qubits stand as a pivotal platform for quantum computing, where scalable fabrication is crucial for building complex quantum circuits. Here, we develop a fabrication process for Nb/Al-AlOx/Nb tri-layer Josephson junctions on 4-inch silicon wafers using full-stepper lithography. Utilizing this process, we have produced both transmon and C-shunt flux qubits. The well-behavedI-Vcharacteristics of junction arrays containing up to 1000 junctions highlight the excellent uniformity and scalability of our process. Furthermore, by introducing a RIE pre-etch before BOE treatment to remove most of the SiO2insulator, we have suppressed dielectric loss and increased the coherence time of the Nb-based transmon qubit by almost 10 times, achieving a quality factor comparable to state-of-the-art Nb-based qubits on sapphire substrates. Given its compatibility with silicon technology, our method paves the way for the integration of multi-qubit processors and the co-fabrication of complex quantum circuits.
We report on the fabrication of Josephson junction and superconducting bridges using a damascene CMP process applied for a first time to superconductors. The demonstrated industrial reliability of damascene CMP processes on large scale semiconductor circuits is a major incentive for our research that should allow large numbers of nanometric Josephson junctions to be fabricated in both Nb and Al, the two main material employed in superconducting quantum computing (qubit) and RSFQ electronics fabrication.We carried out a Chemical-Mechanical Polishing (CMP) process on Nb and Al films deposited on a SiO2 layer patterned with trenches of 100 to 300 nm of nominal depth. The process formed long bridges, 1 to 4 μm wide. The susceptibility and resistive transitions showed that CMP has no observable influence on superconductivity.We have also developed a hybrid technique that uses Al/Al2O3/Al shadow evaporation in the trenches before the damascene CMP process. This allows for high quality “in-situ” junction oxidation with the size reduction benefit provided by the damascene CMP process. We easily reach junctions sizes near 0.5 μm2 which are difficult to fabricate by other methods.We describe these techniques and report on measurements on large bridges and junctions and on the fabrication and measurements of Al and Nb nanobridges.