The performance of superconducting electronic devices such as superconducting quantum bits (qubits) and superconducting quantum interference devices (SQUIDs) strongly relies on high-quality Josephson junctions (JJ) and their integration into surrounding circuit elements. Therefore, a corresponding fabrication technology should allow for the fabrication of all required elements including the JJs, inductances, capacitances and waveguides. For a long time, shadow evaporation technique was the state of the art for the implementation of sub-μ m sized JJs based on aluminum for qubits of high coherence times. Although, the use of a single lithographic step represents a major advantage of this technique. However, shadowing effects limit sample size, device complexity, and thus scalability of the circuitry. To overcome these limitations and to meet the demands of next generation scalable quantum circuits, in this work we introduce our cross -type JJ aluminum technology, where JJs are defined by the overlap of two narrow perpendicular stripes. We discuss the technological challenges, with a focus on our newly developed dry etching process for patterning of the aluminum thin film. Compared to a lift-off based process, this advanced wafer-scale fabrication technology offers a high integration density and the required design flexibility. We will present first results on cross -type aluminum JJs.
The performance of superconducting electronic devices such as superconducting quantum bits (qubits) and superconducting quantum interference devices (SQUIDs) strongly relies on high-quality Josephson junctions (JJ) and their integration into surrounding circuit elements. Therefore, a corresponding fabrication technology should allow for the fabrication of all required elements including the JJs, inductances, capacitances and waveguides. For a long time, shadow evaporation technique was the state of the art for the implementation of sub-μ m sized JJs based on aluminum for qubits of high coherence times. Although, the use of a single lithographic step represents a major advantage of this technique. However, shadowing effects limit sample size, device complexity, and thus scalability of the circuitry. To overcome these limitations and to meet the demands of next generation scalable quantum circuits, in this work we introduce our cross -type JJ aluminum technology, where JJs are defined by the overlap of two narrow perpendicular stripes. We discuss the technological challenges, with a focus on our newly developed dry etching process for patterning of the aluminum thin film. Compared to a lift-off based process, this advanced wafer-scale fabrication technology offers a high integration density and the required design flexibility. We will present first results on cross -type aluminum JJs.
Josephson tunnel junctions represent a key element in superconducting electronics and quantum circuits. For many years, shadow evaporation by means of Dolan-type bridges has been the state-of-the-art for deep sub- micrometer sized structures. Increasing demand in the number of Josephson junctions, e.g. in qubit circuits and travelling wave parametric amplifiers, requests for a wafer-scale fabrication process with precise control of junction parameters and have led to an advanced lift-off technique called Manhattan-type junction technology in recent years. Herein, we report on the development of a 100 mm wafer-scale fabrication technology for deep sub-micrometer sized Al Josephson junctions with linear dimensions down to 180 nm. The critical currentICof the junctions ranges from about 10 to 120 nA scaling with their linear dimensions. Low temperature transport measurements as well as room-temperature characterization has been used forICand process homogeneity determination of series arrays of up to 50 Josephson junctions. We discuss technology parameters such as yield, on-chip and on-wafer reproducibility of the junction's critical currents as well as main process limitations. Moreover, we present experimental results on the characterization of first transmon-type qubits fabricated using this technology.
Fabrication And Characterization Of High-Quality Nb/Al-AlOx/Nb Cross-Type Josephson Tunnel Junctions Utilising CMP-based Planarisation Techniques
Josephson tunnel junctions (JJs) are the fundamental building blocks of today's most advanced superconducting electronic components, such as qubits and superconducting quantum interference devices (SQUIDs). Given the ongoing demand for scalability of these devices on the wafer-scale, it is crucial to control the fabrication process as precisely as possible to ensure uniform quality and reproducibility. Today, window-type JJs are often used in the production of DC SQUIDs and while they are reliable and reproducible, they suffer from alignment inaccuracies caused by photolithography and unavoidable parasitic capacitances, thus limiting the energy sensitivity of DC SQUIDs. These problems can be circumvented by producing JJs with cross-type geometry, which allows for smaller junction areas and eliminates parasitic capacitances. Here we discuss the fabrication of Nb/Al-AlOx/Nb-based cross-type JJs, where the trilayer is embedded in sputter-deposited SiO2 to allow for planarisation of the structures and to ensure the reliable insulation of the sidewalls of the bottom electrode. Instead of lift-off processes that require a lot of time and potentially leave unwanted wings along the edges of microstructures behind that might compromise subsequent layers, we use chemical-mechanical polishing (CMP) for the removal of excess SiO2. This is not only much faster, but produces smooth and uniform surfaces, which in turn effectively improves the reliability of our JJ production process resulting in a high yield of over 90% on wafer-scale. In addition, we discuss the influence of fabrication details on the quality and electrical properties of our JJs with different junction areas down to 1μm×1μm distributed across the wafer and extract the junction specific quality parameters from their IV-characteristics and their Fraunhofer patterns.
Josephson tunnel junctions are the centerpiece of almost any superconducting electronic circuit, including qubits. Typically, the junctions for qubits are fabricated using shadow evaporation techniques to reduce dielectric loss contributions from the superconducting film interfaces. In recent years, however, sub-micrometer scale overlap junctions have started to attract attention. Compared to shadow mask techniques, neither an angle dependent deposition nor free-standing bridges or overlaps are needed, which are significant limitations for wafer-scale processing. This comes at the cost of breaking the vacuum during fabrication, but simplifies integration in multi-layered circuits and implementation of vastly different junction sizes and enables fabrication on a larger scale in an industrially standardized process. In this work, we demonstrate the feasibility of a subtractive process for the fabrication of overlap junctions. In an array of test contacts, we find low aging of the average normal state resistance of only 1.6% over 6 months. We evaluate the coherence properties of the junctions by employing them in superconducting transmon qubits. In time domain experiments, we find that both, the qubit life- and coherence time of our best device, are, on average, greater than 20 μs. Finally, we discuss potential improvements to our technique. This work paves the way toward a more standardized process flow with advanced materials and growth processes, and constitutes an important step for the large scale fabrication of superconducting quantum circuits.
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T1 relaxation times averaging above 50 μs (Q>1.5×106). Current shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. This eliminates a key bottleneck in manufacturing superconducting qubits by reducing the fabrication time and cost. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty 0.5×0.5-cm2 chips, with junction areas ranging between 0.01 and 0.16 μm2. The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4% and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7%–2.5%. We show that 60%–70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.
Sub-μm Josephson Junctions for Superconducting Quantum Devices
For high-performance superconducting quantum devices based on Josephson junctions (JJs), decreasing lateral sizes is of great importance. Fabrication of sub-μm JJs is challenging, due to nonflat surfaces with step heights of up to several 100 nm generated during the fabrication process. We have refined a fabrication process with significantly decreased film thicknesses, resulting in almost flat surfaces at intermediate steps during the JJ definition. In combination with a mix-and-match process, combining electron-beam lithography and conventional photolithography, we can fabricate JJs with lateral dimensions down to 0.023 μm2. We propose this refined process as an alternative to the commonly used chemical-mechanical polishing procedure. Transport measurements of JJs, having critical-current densities ranging from 50 to 104A/cm2, are presented at 4.2 K. Our JJ process yields excellent quality parameters, Rsg/RNup to ~ 50, Vmfrom 15 to 80 mV and Vgapup to 2.81 mV, and also allows the fabrication of high-quality, sub-μm wide, long JJs (LJJs) for the study of Josephson vortex behavior. The developed technique can also be used for similar multilayer processes and is very promising for fabricating sub- μm JJs for quantum devices such as SQUIDs, qubits, and SIS mixers.
In the upcoming decades quantum technologies, especially quantum computation, will have a strong influence on industrial, technological, economic, and social progress and are, therefore, considered to be one of the key technologies. The fundamental building blocks for quantum computation are quantum bits (qubits). The superconducting platform offers one of the most promising implementations due to its monolithic character and potential for scalability. Present research around the world primarily focusses on scaling up the number of qubits, so reliable wafer-scale fabrication technologies are mandatory. In this paper, we present our recent developments on wafer-scale fabrication of superconducting quantum circuits including Josephson junctions by the Manhattan-type technology. We discuss fabrication parameters as well as electrical characterization. For arrays out of 50 Josephson junctions with structure dimensions of 200 nm × 200 nm, we achieve a critical current standard deviation of approx. 3% on-chip and 7% on-wafer. We also show first measurement results of so fabricated transmon-type qubits with relaxation and decoherence times ofT1= 12.5 µs andT2= 15.0 µs, respectively. With an increasing number of superconducting qubits and, thus, their input and read-out lines, new challenges arise: Crosstalk between qubits, unwanted modes in the qubit environment, and required interconnections. One way to counteract is the implementation of low inductance connections across coplanar waveguides. This can be realized by aluminum air bridges. In this paper we discuss the air bridges’ fabrication parameters and the impact on the integrated circuits’ elements, e.g., Josephson junctions. We show electrical and superconducting measurements with critical temperatures and critical currents ofTc> 1.0 K andIc> 0.6 mA, respectively.