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arXiv:1210.1012 · IEEE Transactions on Applied Superconductivity

Sub-$\mu\hbox{m}$ Josephson Junctions for Superconducting Quantum Devices

J. M. Meckbach, Michael Merker, Simon J. Buehler, K. Ilin, Benedikt Neumeier, U. Kienzle, E. Goldobin, R. Kleiner, D. Koelle, M. Siegel

Published Dec 4, 2012• 11 citations
arXivHTMLPDF

Abstract

For high-performance superconducting quantum devices based on Josephson junctions (JJs), decreasing lateral sizes is of great importance. Fabrication of sub-μm JJs is challenging, due to nonflat surfaces with step heights of up to several 100 nm generated during the fabrication process. We have refined a fabrication process with significantly decreased film thicknesses, resulting in almost flat surfaces at intermediate steps during the JJ definition. In combination with a mix-and-match process, combining electron-beam lithography and conventional photolithography, we can fabricate JJs with lateral dimensions down to 0.023 μm2. We propose this refined process as an alternative to the commonly used chemical-mechanical polishing procedure. Transport measurements of JJs, having critical-current densities ranging from 50 to 104A/cm2, are presented at 4.2 K. Our JJ process yields excellent quality parameters, Rsg/RNup to ~ 50, Vmfrom 15 to 80 mV and Vgapup to 2.81 mV, and also allows the fabrication of high-quality, sub-μm wide, long JJs (LJJs) for the study of Josephson vortex behavior. The developed technique can also be used for similar multilayer processes and is very promising for fabricating sub- μm JJs for quantum devices such as SQUIDs, qubits, and SIS mixers.

DOI
10.1109/tasc.2012.2231719

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Sub-μm\mu\hbox{m}μm Josephson Junctions for Superconducting Quantum Devices
For high-performance superconducting quantum devices based on Josephson junctions (JJs), decreasing lateral sizes is of great importance. Fabrication of sub-μm JJs is challenging, due to nonflat surfaces with step heights of up to several 100 nm generated during the fabrication process. We have refined a fabrication process with significantly decreased film thicknesses, resulting in almost flat surfaces at intermediate steps during the JJ definition. In combination with a mix-and-match process, combining electron-beam lithography and conventional photolithography, we can fabricate JJs with lateral dimensions down to 0.023 μm2. We propose this refined process as an alternative to the commonly used chemical-mechanical polishing procedure. Transport measurements of JJs, having critical-current densities ranging from 50 to 104A/cm2, are presented at 4.2 K. Our JJ process yields excellent quality parameters, Rsg/RNup to ~ 50, Vmfrom 15 to 80 mV and Vgapup to 2.81 mV, and also allows the fabrication of high-quality, sub-μm wide, long JJs (LJJs) for the study of Josephson vortex behavior. The developed technique can also be used for similar multilayer processes and is very promising for fabricating sub- μm JJs for quantum devices such as SQUIDs, qubits, and SIS mixers.
The performance of superconducting electronic devices such as superconducting quantum bits (qubits) and superconducting quantum interference devices (SQUIDs) strongly relies on high-quality Josephson junctions (JJ) and their integration into surrounding circuit elements. Therefore, a corresponding fabrication technology should allow for the fabrication of all required elements including the JJs, inductances, capacitances and waveguides. For a long time, shadow evaporation technique was the state of the art for the implementation of sub-μ m sized JJs based on aluminum for qubits of high coherence times. Although, the use of a single lithographic step represents a major advantage of this technique. However, shadowing effects limit sample size, device complexity, and thus scalability of the circuitry. To overcome these limitations and to meet the demands of next generation scalable quantum circuits, in this work we introduce our cross -type JJ aluminum technology, where JJs are defined by the overlap of two narrow perpendicular stripes. We discuss the technological challenges, with a focus on our newly developed dry etching process for patterning of the aluminum thin film. Compared to a lift-off based process, this advanced wafer-scale fabrication technology offers a high integration density and the required design flexibility. We will present first results on cross -type aluminum JJs.
Fabrication And Characterization Of High-Quality Nb/Al-AlOx_xx​/Nb Cross-Type Josephson Tunnel Junctions Utilising CMP-based Planarisation Techniques
Josephson tunnel junctions (JJs) are the fundamental building blocks of today's most advanced superconducting electronic components, such as qubits and superconducting quantum interference devices (SQUIDs). Given the ongoing demand for scalability of these devices on the wafer-scale, it is crucial to control the fabrication process as precisely as possible to ensure uniform quality and reproducibility. Today, window-type JJs are often used in the production of DC SQUIDs and while they are reliable and reproducible, they suffer from alignment inaccuracies caused by photolithography and unavoidable parasitic capacitances, thus limiting the energy sensitivity of DC SQUIDs. These problems can be circumvented by producing JJs with cross-type geometry, which allows for smaller junction areas and eliminates parasitic capacitances. Here we discuss the fabrication of Nb/Al-AlOx/Nb-based cross-type JJs, where the trilayer is embedded in sputter-deposited SiO2_22​ to allow for planarisation of the structures and to ensure the reliable insulation of the sidewalls of the bottom electrode. Instead of lift-off processes that require a lot of time and potentially leave unwanted wings along the edges of microstructures behind that might compromise subsequent layers, we use chemical-mechanical polishing (CMP) for the removal of excess SiO2_22​. This is not only much faster, but produces smooth and uniform surfaces, which in turn effectively improves the reliability of our JJ production process resulting in a high yield of over 90 %90\,\%90% on wafer-scale. In addition, we discuss the influence of fabrication details on the quality and electrical properties of our JJs with different junction areas down to 1 μm×1 μm1\,\mathrm{μm} \times 1\,\mathrm{μm}1μm×1μm distributed across the wafer and extract the junction specific quality parameters from their IV-characteristics and their Fraunhofer patterns.
Several applications of Josephson junctions (JJs) in low-temperature superconducting circuits such as programmable voltage standards and SFQ logical circuits or SQUID sensors require JJs with sub-µm dimensions. A method for preparing superconductor-isolator-superconductor (SIS) JJs as well as superconductor-normal metal-superconductor (SNS) JJs was developed which allows the preparation of both types of junctions by nearly the same technological process. Titanium is used as the normal metal for the SNS JJ. Ti can be anodically oxidized and a technology similar to the well-tried Nb-Al technology for SIS JJs can be applied to the SNS system, too. By electron-beam exposure of a negative deep UV photoresist (ma-N 2400) a stable resist mask is generated which has to withstand the following three self-aligned process steps: etching of the Nb counterelectrode by RIE, isolation by anodization and lifting of a SiO planarization layer. By this process SNS (Nb-Ti-Nb) and SIS (Nb-Al/AlO x -Nb) Josephson junctions with smallest junction areas of 0.49 µm 2 were prepared and characterized by dc measurements and under the influence of microwave irradiation. The Nb-Ti-Nb junctions have I c R n products of 87 µV. They can be used for programmable Josephson voltage standard circuits at frequencies of 70 GHz.
A minimal method to fabricate Al/AlOx_xx​/Al Josephson junctions (JJs) using photolithography and argon etching, before metallization and oxidation, is demonstrated. JJs with areas ranging from 1 to 6 μμμm2^22 can be fabricated and, with the appropriate oxidation conditions, the junction resistance can be varied by $\sim$2 orders of magnitude. Transmission electron microscopy reveals the successful fabrication of JJs with few grain boundaries suggesting reduced energy loss from two-level-systems. Superconducting QUantum Interference Devices (SQUIDs) fabricated from this methodology exhibit reduced resistance variation over multiple chips, compared with electron beam lithography, and the devices can sustain repeated thermal cycles to 10 mK with the excellent flux response remaining unchanged. The quantum applications of this technology are demonstrated by embedding a SQUID resonator into a 3D cavity and parametrically amplifying low photon numbers with gains of $\sim$40 dB. This work establishes the simplest approach to fabricating JJs to date, and it could prove pivotal to the widespread utilization of superconducting circuit-based quantum technologies.
We have developed a combined photolithography and electron-beam lithography fabrication process for sub-\mum to \mum-size Nb/Al-AlOx/Nb Josephson junctions. In order to define the junction size and protect its top electrode during anodic oxidation, we developed and used the new concept of an aluminum hard mask. Josephson junctions of sizes down to 0.5 \mum2 have been fabricated and thoroughly characterized. We found that they have a very high quality, which is witnessed by the IV curves with quality parameters Vm > 50 mV and Vgap = 2.8 mV at 4.2 K, as well as IcRN products of 1.75-1.93 mV obtained at lower temperatures. In order to test the usability of our fabrication process for superconducting quantum bits, we have also designed, fabricated and experimentally investigated phase qubits made of these junctions. We found a relaxation time of T1 = 26 ns and a dephasing time of T2 = 21 ns.