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Superconducting Multilayer Technology for Josephson Devices : Technology, Engineering, Physics, Applications

J. M. Meckbach

Published Jan 1, 2013• 2 citations
Publisher

Abstract

Within this book fabrication processes for high-quality Josephson junctions based on niobium and aluminum oxide as well as niobium nitride and aluminum nitride on various substrates are discussed. Techniques for achieving a planar chip topography and sub-µm lateral dimensions, aiding the realization of sophisticated Josephson devices such as SQUIDs, flux-flow oscillators and long Josephson junctions with artificial phase discontinuities, are presented in detail.

DOI
10.5445/ksp/1000036875

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Applied Physics Letters•Nov 11, 1991•107 citations
Within this book fabrication processes for high-quality Josephson junctions based on niobium and aluminum oxide as well as niobium nitride and aluminum nitride on various substrates are discussed. Techniques for achieving a planar chip topography and sub-µm lateral dimensions, aiding the realization of sophisticated Josephson devices such as SQUIDs, flux-flow oscillators and long Josephson junctions with artificial phase discontinuities, are presented in detail.
A simple and robust process for fabricating low-T/sub c/ Josephson junction integrated circuits has been developed. The process is designed around the Nb/Al/sub 2/O/sub 3/-Al/Nb trilayer, and utilized nine masking steps to form two separate levels of trilayer Josephson junctions, as well as resistors, capacitors, and transmission lines. Materials used for interlayer dielectrics and passivation layers are silicon dioxide and silicon nitride formed by plasma-enhanced chemical vapor deposition (PECVD). The PECVD equipment yields a high deposition rate at moderate substrate temperatures. No degradation of the junction characteristics due to these depositions is seen. The measured loss tangent of this dielectric at 10 GHz using a parallel plate technique is 4.44*10/sup -4/. The dielectric constant of this material is 5.1 in the range of 50 to 400 GHz, measured using an on-chip resonator capacitively coupled to a single shunted Josephson junction. The physical quality of the oxide has been investigated using a variety of tests and has proven to be excellent. A variety of simple circuits using this process technology have been fabricated and tested. More complex circuits are currently under development.
The performance of superconducting electronic devices such as superconducting quantum bits (qubits) and superconducting quantum interference devices (SQUIDs) strongly relies on high-quality Josephson junctions (JJ) and their integration into surrounding circuit elements. Therefore, a corresponding fabrication technology should allow for the fabrication of all required elements including the JJs, inductances, capacitances and waveguides. For a long time, shadow evaporation technique was the state of the art for the implementation of sub-μ m sized JJs based on aluminum for qubits of high coherence times. Although, the use of a single lithographic step represents a major advantage of this technique. However, shadowing effects limit sample size, device complexity, and thus scalability of the circuitry. To overcome these limitations and to meet the demands of next generation scalable quantum circuits, in this work we introduce our cross -type JJ aluminum technology, where JJs are defined by the overlap of two narrow perpendicular stripes. We discuss the technological challenges, with a focus on our newly developed dry etching process for patterning of the aluminum thin film. Compared to a lift-off based process, this advanced wafer-scale fabrication technology offers a high integration density and the required design flexibility. We will present first results on cross -type aluminum JJs.
Research during the initial year of this grant concentrated on fabrication and modelling of long Josephson junction structures. A particular effort was made to understand the basic operating mechanisms of a type of superconducting transistor, the vortex flow transistor, and to optimize its circuit performance. Fabrication techniques were developed using niobium and lead superconductors. These techniques allow rapid production of a variety of device shapes. An optimization of geometric configuration was made to produce the most desirable device characteristics. Amplification was observed at low frequencies and initial coupling circuit designs were made to enable high frequency measurement. Development of potentially more versatile fabrication techniques using niobium and niobium nitride was also begun, as was a simulation study aimed primarily at understanding spatially nonuniform long junction structures.
We have developed a fabrication technique for Josephson junctions that employs a three-dimensional patterned, low-loss substrate instead of commonly used organic resists. The technique enables the fabrication of high-quality trilayer junctions from a wide range of geometries and materials, including high-melting-point superconductors such as tantalum or niobium. The junction electrodes are free from intentionally introduced oxides and organic materials, which are known sources of decoherence. We fabricate and characterize underdamped Nb/AlOx/Nb junctions of different sizes in several geometries.
A simple and robust process for fabricating low-Tc Josephson junction integrated circuits has been developed. The process is designed around the Nb/A1203-Al/Nb trilayer, and utilizes nine masking steps to form two separate levels of trilayer Josephson junctions, as well as resistors, capacitors, and transmission lines. Materials used for interlayer dielectrics and passivation layers are silicon dioxide and silicon nitride formed by Plasma Enhanced Chemical Vapor Deposition (PECVD). The PECVD equipment that we use yields a high deposition rate at moderate substrate temperatures. We see no degradation of the junction characteristics due to these depositions. The measured loss tangent of this dielectric at 10 GHz using a parallel plate technique is 4.44 x 10-4. The dielectric constant of this material is 5.1 in the range of 50 to 400 GHz, measured using an on-chip resonator capacitively coupled to a single shunted Josephson junction. The physical quality of the oxide has been investigated using a variety of tests and has proven to be excellent. We have successfully fabricated and tested a variety of simple circuits using this process technology. Much more complex circuits are currently under development (Fig. 1).
We have demonstrated a new planarized all-refractory technology for low Tc superconductivity (PARTS). With the exception of the Nb-AlOx-Nb trilayer preparation, the processing is done almost exclusively within an advanced Si technology fabrication facility. This approach has allowed us to leverage highly off of existing state-of-the-art lithography, metal etching, materials deposition, and planarization capabilities. Using chemical-mechanical polish as the planarization technique we have fabricated Josephson junctions ranging in size from 0.5–100 μm2. Junction quality is excellent with the figure of merit Vm typically exceeding 70 mV. PARTS has yielded fully functional integrated Josephson devices including magnetometers, gradiometers, and soliton oscillators.