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IEEE Transactions on Magnetics

A simple and robust niobium Josephson junction integrated circuit process

Andrew T. Barfknecht, Rich Ruby, H.L. Ko

Published Mar 1, 1991• 35 citations
Publisher

Abstract

A simple and robust process for fabricating low-T/sub c/ Josephson junction integrated circuits has been developed. The process is designed around the Nb/Al/sub 2/O/sub 3/-Al/Nb trilayer, and utilized nine masking steps to form two separate levels of trilayer Josephson junctions, as well as resistors, capacitors, and transmission lines. Materials used for interlayer dielectrics and passivation layers are silicon dioxide and silicon nitride formed by plasma-enhanced chemical vapor deposition (PECVD). The PECVD equipment yields a high deposition rate at moderate substrate temperatures. No degradation of the junction characteristics due to these depositions is seen. The measured loss tangent of this dielectric at 10 GHz using a parallel plate technique is 4.44*10/sup -4/. The dielectric constant of this material is 5.1 in the range of 50 to 400 GHz, measured using an on-chip resonator capacitively coupled to a single shunted Josephson junction. The physical quality of the oxide has been investigated using a variety of tests and has proven to be excellent. A variety of simple circuits using this process technology have been fabricated and tested. More complex circuits are currently under development.

DOI
10.1109/20.133873

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Arrays of Nb/Al/sub 2/O/sub 3//Nb Josephson tunnel junctions show dc characteristics of high quality when the trilayer is deposited direct on polished Si wafers. Underlayers such as rf-sputtered SiO/sub 2/, can considerably degrade the junction parameters. These results suggest that voltage standard chips should be produced with a cover instead of a groundplane. First results of attenuation measurements on such circuits are presented and discussed. Furthermore, a new and more simple fabrication process without a window-insulating layer and only two photolithographic steps is presented. Arrays of several thousands of junctions showed no problems of any kind with trapped flux.>

IEEE Transactions on Applied Superconductivity•Jun 1, 1995•23 citations
A simple and robust process for fabricating low-T/sub c/ Josephson junction integrated circuits has been developed. The process is designed around the Nb/Al/sub 2/O/sub 3/-Al/Nb trilayer, and utilized nine masking steps to form two separate levels of trilayer Josephson junctions, as well as resistors, capacitors, and transmission lines. Materials used for interlayer dielectrics and passivation layers are silicon dioxide and silicon nitride formed by plasma-enhanced chemical vapor deposition (PECVD). The PECVD equipment yields a high deposition rate at moderate substrate temperatures. No degradation of the junction characteristics due to these depositions is seen. The measured loss tangent of this dielectric at 10 GHz using a parallel plate technique is 4.44*10/sup -4/. The dielectric constant of this material is 5.1 in the range of 50 to 400 GHz, measured using an on-chip resonator capacitively coupled to a single shunted Josephson junction. The physical quality of the oxide has been investigated using a variety of tests and has proven to be excellent. A variety of simple circuits using this process technology have been fabricated and tested. More complex circuits are currently under development.
A simple and robust process for fabricating low-Tc Josephson junction integrated circuits has been developed. The process is designed around the Nb/A1203-Al/Nb trilayer, and utilizes nine masking steps to form two separate levels of trilayer Josephson junctions, as well as resistors, capacitors, and transmission lines. Materials used for interlayer dielectrics and passivation layers are silicon dioxide and silicon nitride formed by Plasma Enhanced Chemical Vapor Deposition (PECVD). The PECVD equipment that we use yields a high deposition rate at moderate substrate temperatures. We see no degradation of the junction characteristics due to these depositions. The measured loss tangent of this dielectric at 10 GHz using a parallel plate technique is 4.44 x 10-4. The dielectric constant of this material is 5.1 in the range of 50 to 400 GHz, measured using an on-chip resonator capacitively coupled to a single shunted Josephson junction. The physical quality of the oxide has been investigated using a variety of tests and has proven to be excellent. We have successfully fabricated and tested a variety of simple circuits using this process technology. Much more complex circuits are currently under development (Fig. 1).
We have developed a fabrication technology for superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels includes 3 Nb superconducting layers and a Mo resistor layer. The influence of deposition parameters on film stress, electrical properties, and surface roughness were studied systematically. High quality Nb, Al, Mo, and SiO2films were successfully deposited for the subsequent fabrication of circuits. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistanceRshof 2 Ω, followed by the deposition of Nb/Al-AlOx/Nb trilayer Josephson-junction. The target critical current densityJcwas set at 6 kA/cm2. Small-scale circuits such as our standard library cells have been successfully fabricated and tested, confirming the capability of our fabrication technology for superconducting integrated circuits.
Development of 15kA/cm2^22 Fabrication Process for Superconducting Integrated Digital Circuits
A new fabrication process for superconducting integrated digital circuits is reported. We have developed the "SIMIT Nb04" fabrication technique for superconducting integrated circuits with Nb-based Josephson junctions based on the validated "SIMIT Nb03" process and Chemical Mechanical Planarization (CMP) technology. Seven Nb superconducting layers and one Mo resistor layer are included in the "SIMIT Nb04" process with 19 mask levels. The device structure is composed of active layers including junctions at the bottom, two passive transmission line (PTL) layers in the middle and a DC power layer at the top. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance Rsh of 3 ΩΩΩ, followed by the deposition of Nb/Al-AlOx_xx​/Nb trilayer Josephson-junction with a target critical current density Jc at 15 kA/cm2^22. To increase the Al-AlOx_xx​ barrier layer etching's repeatability, an additional barrier protection layer was applied. To accomplish high-quality planarization, we created a planarization procedure coupled with dummy filling. To assess the process dependability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and monitored. The successful manufacturing and testing of a few small-scale circuits, like our standard library cells, further attests to the viability of our fabrication process for superconducting integrated circuits.
We present the latest development of an Nb/Al-AlOx/Nb Josephson junction fabrication process for superconducting integrated circuits at SIMIT. Our fabrication process has four niobium superconducting layers and one Ti/Pd resistor layer with 1.0 Ω/square sheet resistor for junction shunting and circuit biasing. Critical current density Jcof the junctions is controlled from 30 A/cm2to 10 kA/cm2by exposing aluminum layer to pure or mixed O2atmosphere. Correlation between measured Jcand exposure conditions has been established. Average quality factor (Rsg/Rn) of the junctions in our process is larger than 20 with subgap leakage factor (Vm) beyond 30 mV. Critical current uniformity is obtained according to the switching current (Is) distribution of a 1000-JJ array. Measured standard deviation sigma of Isis less than 4% over the 100-mm wafer. Plasma resonance in a large Josephson junction is used to measure specific capacitance (Cs) of the junction. Sheet inductances of superconducting niobium strip-lines are extracted by a SQUID diagnose circuit and the measured results show good agreement with our design values.
For reliable fabrication of Nb/AlO/sub x//Nb Josephson integrated circuits, a combination of anodization and reactive ion etching techniques was used to make various sizes of high-quality Nb/AlO/sub x//Nb Josephson tunnel junctions with J/sub c/ as high as 5000 A/cm/sup 2/ and V/sub m/(2 mV) as large as 60 mV at 4.2 K. A ten-level process on Nb/AlO/sub x//Nb trilayers with J/sub c/ of 1500 A/cm/sup 2/ was used to fabricate a functional 12-b A/D converter. This circuit included 2.7- mu m-diameter junctions defined by anodization and 5- mu m-diameter junctions defined by reactive ion etching using Nb/sub 2/O/sub 5/ and Al as etch stops. A lift-off process with image-reversal photoresist was used to define SiO/sub 2/ insulators, Mo resistors, and Au resistors. Mo resistor values were adjusted by reactive ion etching. Measurements of the completed circuit show that all circuit components had correct values to well within design tolerance.
Arrays of Nb/Al/sub 2/O/sub 3//Nb Josephson tunnel junctions show dc characteristics of high quality when the trilayer is deposited direct on polished Si wafers. Underlayers such as rf-sputtered SiO/sub 2/, can considerably degrade the junction parameters. These results suggest that voltage standard chips should be produced with a cover instead of a groundplane. First results of attenuation measurements on such circuits are presented and discussed. Furthermore, a new and more simple fabrication process without a window-insulating layer and only two photolithographic steps is presented. Arrays of several thousands of junctions showed no problems of any kind with trapped flux.>