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IEEE Transactions on Magnetics

Fabrication of a 12-bit A/D converter using Nb/AlO/sub x//Nb Josephson junctions

J.H. Kang, Donald L. Miller, John X. Przybysz, M. A. Janocko

Published Mar 1, 1991• 12 citations
Publisher

Abstract

For reliable fabrication of Nb/AlO/sub x//Nb Josephson integrated circuits, a combination of anodization and reactive ion etching techniques was used to make various sizes of high-quality Nb/AlO/sub x//Nb Josephson tunnel junctions with J/sub c/ as high as 5000 A/cm/sup 2/ and V/sub m/(2 mV) as large as 60 mV at 4.2 K. A ten-level process on Nb/AlO/sub x//Nb trilayers with J/sub c/ of 1500 A/cm/sup 2/ was used to fabricate a functional 12-b A/D converter. This circuit included 2.7- mu m-diameter junctions defined by anodization and 5- mu m-diameter junctions defined by reactive ion etching using Nb/sub 2/O/sub 5/ and Al as etch stops. A lift-off process with image-reversal photoresist was used to define SiO/sub 2/ insulators, Mo resistors, and Au resistors. Mo resistor values were adjusted by reactive ion etching. Measurements of the completed circuit show that all circuit components had correct values to well within design tolerance.

DOI
10.1109/20.133995

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High-quality sub-micron Nb trilayer tunnel junctions for a 100 GHz SIS receiver

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A modified SNIP process was used to fabricate high-quality 0.5, 2, and 4 mu m/sup 2/ small-area Nb/AlO/sub x//Nb trilayer tunnel junctions with current densities as large as 5000 A/cm/sup 2/. The average junction quality factors for the junctions at 4.4 K were V/sub m/(2 mV)=39 mV for J/sub c/=3000 A/cm/sup 2/ and V/sub m/ (2 mV)=27 mV for J/sub c/=5000 A/cm/sup 2/. The best values of V/sub m/ obtained were 50 mV for J/sub c/=3000 A/cm/sup 2/ and 41 mV for J/sub c/=5000 A/cm/sup 2/. These devices were designed and fabricated for use in a W-band mixer receiver. The substrate was 50- mu m-thick fused or crystal quartz. Special methods were developed for handling such thin insulating substrates and patterning films. The fabrication process was self-aligned and used SiO/sub 2/ instead of anodized Nb as the thick insulator. SiO/sub 2/ isolated the junction area and defined the opening for contact to the Nb wiring layer. The authors have fabricated series arrays of up to 12 junctions, with individual junction areas of 0.5 mu m/sup 2/. The array I-V quality was not degraded compared to that of an individual junction.

IEEE Transactions on Magnetics•Mar 1, 1991•17 citations
For reliable fabrication of Nb/AlO/sub x//Nb Josephson integrated circuits, a combination of anodization and reactive ion etching techniques was used to make various sizes of high-quality Nb/AlO/sub x//Nb Josephson tunnel junctions with J/sub c/ as high as 5000 A/cm/sup 2/ and V/sub m/(2 mV) as large as 60 mV at 4.2 K. A ten-level process on Nb/AlO/sub x//Nb trilayers with J/sub c/ of 1500 A/cm/sup 2/ was used to fabricate a functional 12-b A/D converter. This circuit included 2.7- mu m-diameter junctions defined by anodization and 5- mu m-diameter junctions defined by reactive ion etching using Nb/sub 2/O/sub 5/ and Al as etch stops. A lift-off process with image-reversal photoresist was used to define SiO/sub 2/ insulators, Mo resistors, and Au resistors. Mo resistor values were adjusted by reactive ion etching. Measurements of the completed circuit show that all circuit components had correct values to well within design tolerance.
Nb/Al–AlO x /Nb tunnel junctions are often used in the studies of macroscopic quantum phenomena and superconducting qubit applications of the Josephson devices. In this work, we describe a convenient and reliable process using electron beam lithography for the fabrication of high-quality, submicron-sized Nb/Al–AlO x /Nb Josephson junctions. The technique follows the well-known selective Nb etching process and produces high-quality junctions with V m = 100 mV at 2.3 K for the typical critical current density of 2.2 kA/cm 2 , which can be adjusted by controlling the oxygen pressure and oxidation time during the formation of the tunnelling barrier. We present the results of the temperature dependence of the sub-gap current and in-plane magnetic-field dependence of the critical current, and compare them with the theoretical predictions.
Researches on the fabrication of ~ 0.1 × 0.1 μ m 2 superconductor–insulator–superconductor (SIS) Josephson junctions are reviewed. Today, a typical dimension is 1–10 μm for Josephson junctions in superconducting integrated circuits. These Josephson junctions are defined by well-established photolithographic technology with reactive ion etching (RIE), and for the superconductor, Nb is almost always used. The merits of Nb include the facts that the superconducting transition temperature Tc of Nb (9.2 K ) is higher than the boiling point of He (4.2 K ), and that Nb has excellent stability against thermal cycling between room temperature and liquid- He temperature. For the fabrication of ~ 0.1 × 0.1 μ m 2 junctions, on the other hand, there is a standard process with electron-beam lithography, shadow evaporation, and lift-off. This process works well for Al (Tc = 1.2 K ), however, it is not ideal for Nb . The scope of this brief review is the nanoscale junction with Nb electrodes. We will look at the efforts of optimizing the standard lift-off process for Nb , electron-beam-lithographic versions of the Nb Josephson-junction technology, focused-ion-beam (FIB) etching as a convenient alternative to electron-beam lithography and RIE, etc. In order to characterize nanoscale tunnel junctions, the single-charge transistor has been often fabricated. Therefore, a summary of its theoretical transport properties is also included.
Development of 15kA/cm2^22 Fabrication Process for Superconducting Integrated Digital Circuits
A new fabrication process for superconducting integrated digital circuits is reported. We have developed the "SIMIT Nb04" fabrication technique for superconducting integrated circuits with Nb-based Josephson junctions based on the validated "SIMIT Nb03" process and Chemical Mechanical Planarization (CMP) technology. Seven Nb superconducting layers and one Mo resistor layer are included in the "SIMIT Nb04" process with 19 mask levels. The device structure is composed of active layers including junctions at the bottom, two passive transmission line (PTL) layers in the middle and a DC power layer at the top. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance Rsh of 3 ΩΩΩ, followed by the deposition of Nb/Al-AlOx_xx​/Nb trilayer Josephson-junction with a target critical current density Jc at 15 kA/cm2^22. To increase the Al-AlOx_xx​ barrier layer etching's repeatability, an additional barrier protection layer was applied. To accomplish high-quality planarization, we created a planarization procedure coupled with dummy filling. To assess the process dependability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and monitored. The successful manufacturing and testing of a few small-scale circuits, like our standard library cells, further attests to the viability of our fabrication process for superconducting integrated circuits.
We have developed a fabrication technology for superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels includes 3 Nb superconducting layers and a Mo resistor layer. The influence of deposition parameters on film stress, electrical properties, and surface roughness were studied systematically. High quality Nb, Al, Mo, and SiO2films were successfully deposited for the subsequent fabrication of circuits. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistanceRshof 2 Ω, followed by the deposition of Nb/Al-AlOx/Nb trilayer Josephson-junction. The target critical current densityJcwas set at 6 kA/cm2. Small-scale circuits such as our standard library cells have been successfully fabricated and tested, confirming the capability of our fabrication technology for superconducting integrated circuits.
A simple and robust process for fabricating low-T/sub c/ Josephson junction integrated circuits has been developed. The process is designed around the Nb/Al/sub 2/O/sub 3/-Al/Nb trilayer, and utilized nine masking steps to form two separate levels of trilayer Josephson junctions, as well as resistors, capacitors, and transmission lines. Materials used for interlayer dielectrics and passivation layers are silicon dioxide and silicon nitride formed by plasma-enhanced chemical vapor deposition (PECVD). The PECVD equipment yields a high deposition rate at moderate substrate temperatures. No degradation of the junction characteristics due to these depositions is seen. The measured loss tangent of this dielectric at 10 GHz using a parallel plate technique is 4.44*10/sup -4/. The dielectric constant of this material is 5.1 in the range of 50 to 400 GHz, measured using an on-chip resonator capacitively coupled to a single shunted Josephson junction. The physical quality of the oxide has been investigated using a variety of tests and has proven to be excellent. A variety of simple circuits using this process technology have been fabricated and tested. More complex circuits are currently under development.
A modified SNIP process was used to fabricate high-quality 0.5, 2, and 4 mu m/sup 2/ small-area Nb/AlO/sub x//Nb trilayer tunnel junctions with current densities as large as 5000 A/cm/sup 2/. The average junction quality factors for the junctions at 4.4 K were V/sub m/(2 mV)=39 mV for J/sub c/=3000 A/cm/sup 2/ and V/sub m/ (2 mV)=27 mV for J/sub c/=5000 A/cm/sup 2/. The best values of V/sub m/ obtained were 50 mV for J/sub c/=3000 A/cm/sup 2/ and 41 mV for J/sub c/=5000 A/cm/sup 2/. These devices were designed and fabricated for use in a W-band mixer receiver. The substrate was 50- mu m-thick fused or crystal quartz. Special methods were developed for handling such thin insulating substrates and patterning films. The fabrication process was self-aligned and used SiO/sub 2/ instead of anodized Nb as the thick insulator. SiO/sub 2/ isolated the junction area and defined the opening for contact to the Nb wiring layer. The authors have fabricated series arrays of up to 12 junctions, with individual junction areas of 0.5 mu m/sup 2/. The array I-V quality was not degraded compared to that of an individual junction.