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arXiv:2011.06272 · IEEE Transactions on Applied Superconductivity

Development of Multi-Layer Fabrication Process for SFQ Large Scale Integrated Digital Circuits

Liliang Ying, Xue Zhang, Minghui Niu, Jie Ren, Wei Peng, Masaaki Maezawa, Zhen Wang

Published Mar 11, 2021• 76 citations
arXivHTMLPDF

Abstract

We have developed a fabrication technology for superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels includes 3 Nb superconducting layers and a Mo resistor layer. The influence of deposition parameters on film stress, electrical properties, and surface roughness were studied systematically. High quality Nb, Al, Mo, and SiO2films were successfully deposited for the subsequent fabrication of circuits. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistanceRshof 2 Ω, followed by the deposition of Nb/Al-AlOx/Nb trilayer Josephson-junction. The target critical current densityJcwas set at 6 kA/cm2. Small-scale circuits such as our standard library cells have been successfully fabricated and tested, confirming the capability of our fabrication technology for superconducting integrated circuits.

DOI
10.1109/tasc.2021.3065277

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We have developed a fabrication technology for superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels includes 3 Nb superconducting layers and a Mo resistor layer. The influence of deposition parameters on film stress, electrical properties, and surface roughness were studied systematically. High quality Nb, Al, Mo, and SiO2films were successfully deposited for the subsequent fabrication of circuits. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistanceRshof 2 Ω, followed by the deposition of Nb/Al-AlOx/Nb trilayer Josephson-junction. The target critical current densityJcwas set at 6 kA/cm2. Small-scale circuits such as our standard library cells have been successfully fabricated and tested, confirming the capability of our fabrication technology for superconducting integrated circuits.
Development of 15kA/cm2^22 Fabrication Process for Superconducting Integrated Digital Circuits
A new fabrication process for superconducting integrated digital circuits is reported. We have developed the "SIMIT Nb04" fabrication technique for superconducting integrated circuits with Nb-based Josephson junctions based on the validated "SIMIT Nb03" process and Chemical Mechanical Planarization (CMP) technology. Seven Nb superconducting layers and one Mo resistor layer are included in the "SIMIT Nb04" process with 19 mask levels. The device structure is composed of active layers including junctions at the bottom, two passive transmission line (PTL) layers in the middle and a DC power layer at the top. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance Rsh of 3 ΩΩΩ, followed by the deposition of Nb/Al-AlOx_xx​/Nb trilayer Josephson-junction with a target critical current density Jc at 15 kA/cm2^22. To increase the Al-AlOx_xx​ barrier layer etching's repeatability, an additional barrier protection layer was applied. To accomplish high-quality planarization, we created a planarization procedure coupled with dummy filling. To assess the process dependability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and monitored. The successful manufacturing and testing of a few small-scale circuits, like our standard library cells, further attests to the viability of our fabrication process for superconducting integrated circuits.
We present the latest development of an Nb/Al-AlOx/Nb Josephson junction fabrication process for superconducting integrated circuits at SIMIT. Our fabrication process has four niobium superconducting layers and one Ti/Pd resistor layer with 1.0 Ω/square sheet resistor for junction shunting and circuit biasing. Critical current density Jcof the junctions is controlled from 30 A/cm2to 10 kA/cm2by exposing aluminum layer to pure or mixed O2atmosphere. Correlation between measured Jcand exposure conditions has been established. Average quality factor (Rsg/Rn) of the junctions in our process is larger than 20 with subgap leakage factor (Vm) beyond 30 mV. Critical current uniformity is obtained according to the switching current (Is) distribution of a 1000-JJ array. Measured standard deviation sigma of Isis less than 4% over the 100-mm wafer. Plasma resonance in a large Josephson junction is used to measure specific capacitance (Cs) of the junction. Sheet inductances of superconducting niobium strip-lines are extracted by a SQUID diagnose circuit and the measured results show good agreement with our design values.
We have developed a 6-kA/cm superconducting integrated circuit fabrication process toward large-scale single flux quantum digital circuits. To evaluate the process reliability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and tested. Fabrication parameters, for example, film thicknesses and etched depths of the layers, were measured by testing specific patterns during fabrication. Design parameters such as the critical current density Jc, normal-state resistance Rnand actual sizes of Josephson junctions, the sheet resistance of Mo resistor Rsh, and the penetration depth of Nb films were evaluated by electrically characterizing PCM circuits after fabrication. We also monitored superconducting critical currents for vias and Nb lines, and insulation properties between the metal layers systematically.
The Superconductivity Research Laboratory has successfully fabricated large quantities of single flux quantum (SFQ) large scale integrated circuits, including several thousands of Josephson junctions (JJs). Using a Jc = 2.5 kA cm−2 process in which the number of Nb layers was four and the minimum JJ size was 2 µm square. We developed a new advanced fabrication process that produced a Jc = 10 kA cm−2, nine Nb layers and a minimum JJ size of 1 µm square. The increase in the number of Nb layers was achieved by using a planarization technique. The target of our next generation process is a Jc = 40 kA cm−2 with a 0.5 µm square for the minimum junction size. This specification will be achieved by using advanced semiconductor technologies. This process will enable SFQ circuits to be produced with one million JJs on a chip and achieve a clock frequency greater than 100 GHz.
A simple and robust process for fabricating low-T/sub c/ Josephson junction integrated circuits has been developed. The process is designed around the Nb/Al/sub 2/O/sub 3/-Al/Nb trilayer, and utilized nine masking steps to form two separate levels of trilayer Josephson junctions, as well as resistors, capacitors, and transmission lines. Materials used for interlayer dielectrics and passivation layers are silicon dioxide and silicon nitride formed by plasma-enhanced chemical vapor deposition (PECVD). The PECVD equipment yields a high deposition rate at moderate substrate temperatures. No degradation of the junction characteristics due to these depositions is seen. The measured loss tangent of this dielectric at 10 GHz using a parallel plate technique is 4.44*10/sup -4/. The dielectric constant of this material is 5.1 in the range of 50 to 400 GHz, measured using an on-chip resonator capacitively coupled to a single shunted Josephson junction. The physical quality of the oxide has been investigated using a variety of tests and has proven to be excellent. A variety of simple circuits using this process technology have been fabricated and tested. More complex circuits are currently under development.
We have been developing a 10 kA cm −2 Nb advanced fabrication process to make larger scale and higher speed SFQ circuits that have over 100k junctions. The main challenges in implementing this process are related to increasing the critical current density of junctions, decreasing design rules and increasing the number of Nb layers. We have proposed a planarized multi-layer structure, which consists of a Nb/AlO x /Nb junction layer, Nb wiring layers, Nb shield layers, a Nb layer for dc power, a Nb ground plane, SiO 2 insulator layers and a Mo resistor layer. In fabricating this multi-layer structure, we have developed a new planarization technology which enables the flattening of the SiO 2 insulator surface over the Nb wiring layer independent of the pattern sizes of the Nb wirings. This planarization technology consists of SiO 2 bias sputtering, reactive ion etching with a reversal mask of the Nb wiring and mechanical polishing planarization. The SEM photographs showed excellent flatness for the planarized multi-layer structure.