We have developed a 6-kA/cm superconducting integrated circuit fabrication process toward large-scale single flux quantum digital circuits. To evaluate the process reliability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and tested. Fabrication parameters, for example, film thicknesses and etched depths of the layers, were measured by testing specific patterns during fabrication. Design parameters such as the critical current density Jc, normal-state resistance Rnand actual sizes of Josephson junctions, the sheet resistance of Mo resistor Rsh, and the penetration depth of Nb films were evaluated by electrically characterizing PCM circuits after fabrication. We also monitored superconducting critical currents for vias and Nb lines, and insulation properties between the metal layers systematically.
We have developed a 6-kA/cm superconducting integrated circuit fabrication process toward large-scale single flux quantum digital circuits. To evaluate the process reliability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and tested. Fabrication parameters, for example, film thicknesses and etched depths of the layers, were measured by testing specific patterns during fabrication. Design parameters such as the critical current density Jc, normal-state resistance Rnand actual sizes of Josephson junctions, the sheet resistance of Mo resistor Rsh, and the penetration depth of Nb films were evaluated by electrically characterizing PCM circuits after fabrication. We also monitored superconducting critical currents for vias and Nb lines, and insulation properties between the metal layers systematically.
Development of 15kA/cm2 Fabrication Process for Superconducting Integrated Digital Circuits
A new fabrication process for superconducting integrated digital circuits is reported. We have developed the "SIMIT Nb04" fabrication technique for superconducting integrated circuits with Nb-based Josephson junctions based on the validated "SIMIT Nb03" process and Chemical Mechanical Planarization (CMP) technology. Seven Nb superconducting layers and one Mo resistor layer are included in the "SIMIT Nb04" process with 19 mask levels. The device structure is composed of active layers including junctions at the bottom, two passive transmission line (PTL) layers in the middle and a DC power layer at the top. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance Rsh of 3 Ω, followed by the deposition of Nb/Al-AlOx/Nb trilayer Josephson-junction with a target critical current density Jc at 15 kA/cm2. To increase the Al-AlOx barrier layer etching's repeatability, an additional barrier protection layer was applied. To accomplish high-quality planarization, we created a planarization procedure coupled with dummy filling. To assess the process dependability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and monitored. The successful manufacturing and testing of a few small-scale circuits, like our standard library cells, further attests to the viability of our fabrication process for superconducting integrated circuits.
We have developed a fabrication technology for superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels includes 3 Nb superconducting layers and a Mo resistor layer. The influence of deposition parameters on film stress, electrical properties, and surface roughness were studied systematically. High quality Nb, Al, Mo, and SiO2films were successfully deposited for the subsequent fabrication of circuits. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistanceRshof 2 Ω, followed by the deposition of Nb/Al-AlOx/Nb trilayer Josephson-junction. The target critical current densityJcwas set at 6 kA/cm2. Small-scale circuits such as our standard library cells have been successfully fabricated and tested, confirming the capability of our fabrication technology for superconducting integrated circuits.
We developed a process for fabricating nitride superconductor-based superconducting qubits monolithically integrated with a single flux quantum (SFQ)-based readout and control circuits. Since we used a Josephson junction (JJ) made of an NbN/AlN/NbN tri-layer, including a critical current density (Jc) of 50 A/cm2as the suitable material for superconducting qubits and SFQ readout/control circuits operating at 20 mK, the JJs for both the qubits and the SFQ circuits could simultaneously be fabricated. The device structure was also composed of three superconductive layers, comprising two superconductive layers as wiring layers and other layers as the top ground plane. Then, we used a Pd film as the resistive layer, which is required as the shunt resistors and the bias resistors for the SFQ control circuits, followed by an investigation of the properties of NbN/AlN/NbN epitaxial junctions and evaluation of the sheet inductance of the base NbN and wiring NbTiN layer. Our results showed the successful fabrication of a JJ with a sufficiently low leakage current and aJcof around 50 A/cm2, which was close to the target value. Furthermore, the evaluated sheet inductance exceeded 1 pH, which was several times larger than the values obtained for Nb-integrated circuits.
We implemented, optimized, and fully tested a superconducting Josephson junction fabrication process over multiple runs tailored for integrated digital circuits that are used for control and readout of superconducting qubits operating at millikelvin temperatures. This process was optimized for highly energy efficient rapid single flux quantum (ERSFQ) circuits with critical currents reduced by a factor of ∼10 as compared to those operated at 4.2 K. Specifically, it implemented Josephson junctions with 10 μA unit critical current fabricated with 10 μA/μm2 critical current density. In order to circumvent the substantial size increase in the SFQ circuit inductors, we employed an NbN high kinetic inductance layer with 8.5 pH/sq sheet inductance. Similarly, to maintain the small size of junction resistive shunts, we used a non-superconducting PdAu alloy with 4.0 Ω/sq sheet resistance. For integration with quantum circuits in a multi-chip module, 5 and 10 μm height bump processes were also optimized. To keep the fabrication process in check, we developed and thoroughly tested a comprehensive process control monitor chip set.
Using a fully automated cryogenic wafer prober, we measured superconductor fabrication process control monitors and simple integrated circuits on 200-mm wafers at 4.4 K, including SQIF-based magnetic field sensors, SQUID-based circuits for measuring inductors, Nb/Al-AlOx/Nb Josephson junctions, test structures for measuring critical current of superconducting wires and vias, resistors, etc., to demonstrate the feasibility of using the system for characterizing niobium superconducting devices and integrated circuits on a wafer scale. Data on the wafer-scale distributions of the residual magnetic field, junction tunnel resistance, energy gap, inductance of multiple Nb layers, and critical currents of interlayer vias are presented. A comparison with existing models is made. The wafers were fabricated in the SFQ5ee process, the fully planarized process with eight niobium layers and a layer of kinetic inductors, developed for superconductor electronics at MIT Lincoln Laboratory, Lexington, MA, USA. The cryogenic wafer prober was developed at HPD/FormFactor, Inc., Boulder, CO, USA.
Using a fully automated cryogenic wafer prober, we measured superconductor fabrication process control monitors and simple integrated circuits on 200 mm wafers at 4.2 K, including Nb/Al-AlOx/Nb Josephson junctions, SQUID-based circuits for measuring inductors, test structures for measuring critical current of superconducting wires and vias, resistors, etc., to demonstrate the feasibility of using the system for characterizing niobium superconducting devices and integrated circuits on a wafer scale. The data on the wafer-scale distributions of the junction tunnel resistance, energy gap, inductance of Nb layers, critical currents of interlayer vias are presented. The wafers were fabricated in the SFQ5ee process, the fully planarized process with eight niobium layers and a layer of kinetic inductors, developed for superconductor electronics at MIT Lincoln Laboratory. The cryogenic wafer prober was developed at HPD/ FormFactor, Inc.