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Wafer-Scale Characterization of a Superconductor Integrated Circuit Process, Using a Cryogenic Wafer Prober.

Joshua T. West, A. Kurlej, Alex Wynn, Chad Rogers, M.A. Gouker, Sergey K. Tolpygo

Published Dec 1, 2021• 2 citations
OpenAlex

Abstract

Using a fully automated cryogenic wafer prober, we measured superconductor fabrication process control monitors and simple integrated circuits on 200 mm wafers at 4.2 K, including Nb/Al-AlOx/Nb Josephson junctions, SQUID-based circuits for measuring inductors, test structures for measuring critical current of superconducting wires and vias, resistors, etc., to demonstrate the feasibility of using the system for characterizing niobium superconducting devices and integrated circuits on a wafer scale. The data on the wafer-scale distributions of the junction tunnel resistance, energy gap, inductance of Nb layers, critical currents of interlayer vias are presented. The wafers were fabricated in the SFQ5ee process, the fully planarized process with eight niobium layers and a layer of kinetic inductors, developed for superconductor electronics at MIT Lincoln Laboratory. The cryogenic wafer prober was developed at HPD/ FormFactor, Inc.

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Using a fully automated cryogenic wafer prober, we measured superconductor fabrication process control monitors and simple integrated circuits on 200 mm wafers at 4.2 K, including Nb/Al-AlOx/Nb Josephson junctions, SQUID-based circuits for measuring inductors, test structures for measuring critical current of superconducting wires and vias, resistors, etc., to demonstrate the feasibility of using the system for characterizing niobium superconducting devices and integrated circuits on a wafer scale. The data on the wafer-scale distributions of the junction tunnel resistance, energy gap, inductance of Nb layers, critical currents of interlayer vias are presented. The wafers were fabricated in the SFQ5ee process, the fully planarized process with eight niobium layers and a layer of kinetic inductors, developed for superconductor electronics at MIT Lincoln Laboratory. The cryogenic wafer prober was developed at HPD/ FormFactor, Inc.
Using a fully automated cryogenic wafer prober, we measured superconductor fabrication process control monitors and simple integrated circuits on 200-mm wafers at 4.4 K, including SQIF-based magnetic field sensors, SQUID-based circuits for measuring inductors, Nb/Al-AlOx/Nb Josephson junctions, test structures for measuring critical current of superconducting wires and vias, resistors, etc., to demonstrate the feasibility of using the system for characterizing niobium superconducting devices and integrated circuits on a wafer scale. Data on the wafer-scale distributions of the residual magnetic field, junction tunnel resistance, energy gap, inductance of multiple Nb layers, and critical currents of interlayer vias are presented. A comparison with existing models is made. The wafers were fabricated in the SFQ5ee process, the fully planarized process with eight niobium layers and a layer of kinetic inductors, developed for superconductor electronics at MIT Lincoln Laboratory, Lexington, MA, USA. The cryogenic wafer prober was developed at HPD/FormFactor, Inc., Boulder, CO, USA.
We present the latest development of an Nb/Al-AlOx/Nb Josephson junction fabrication process for superconducting integrated circuits at SIMIT. Our fabrication process has four niobium superconducting layers and one Ti/Pd resistor layer with 1.0 Ω/square sheet resistor for junction shunting and circuit biasing. Critical current density Jcof the junctions is controlled from 30 A/cm2to 10 kA/cm2by exposing aluminum layer to pure or mixed O2atmosphere. Correlation between measured Jcand exposure conditions has been established. Average quality factor (Rsg/Rn) of the junctions in our process is larger than 20 with subgap leakage factor (Vm) beyond 30 mV. Critical current uniformity is obtained according to the switching current (Is) distribution of a 1000-JJ array. Measured standard deviation sigma of Isis less than 4% over the 100-mm wafer. Plasma resonance in a large Josephson junction is used to measure specific capacitance (Cs) of the junction. Sheet inductances of superconducting niobium strip-lines are extracted by a SQUID diagnose circuit and the measured results show good agreement with our design values.
Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90° bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. It has been found that the inductance per unit length of stripline and microstrip line inductors continues to grow as the inductor linewidth is reduced deep into the submicron range to the widths comparable to the film thickness and magnetic field penetration depth. It is shown that the linewidth reduction does not lead to widening of the parameter spread due to diminishing sensitivity of the inductance to the linewidth and dielectric thickness. The experimental results were compared with numeric inductance extraction using commercial software and freeware, and a good agreement was found for 3-D inductance extractors. Methods of further miniaturization of circuit inductors for achieving circuit densities> 106Josephson junctions per cm2are discussed.
We have developed a 6-kA/cm superconducting integrated circuit fabrication process toward large-scale single flux quantum digital circuits. To evaluate the process reliability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and tested. Fabrication parameters, for example, film thicknesses and etched depths of the layers, were measured by testing specific patterns during fabrication. Design parameters such as the critical current density Jc, normal-state resistance Rnand actual sizes of Josephson junctions, the sheet resistance of Mo resistor Rsh, and the penetration depth of Nb films were evaluated by electrically characterizing PCM circuits after fabrication. We also monitored superconducting critical currents for vias and Nb lines, and insulation properties between the metal layers systematically.
Coulomb blockade thermometers (CBTs) have attracted more interest in recent years, as the demand for sub-one Kelvin thermometry has increased, especially due to the prevalence of dilution refrigerators in research and applications in quantum technology. CBTs can be operated both as a primary thermometer, requiring no prior calibration, or as a simple resistance thermometer in the secondary mode after calibration. As new scalable fabrication processes for quantum devices and cryogenic electronics are being developed, cryogenic wafer characterization methods must also scale up to provide statistical data on device parameters. Currently, characterization throughput of cryogenic devices is limited by the turnover time and sample capacity of traditional cryostats, where a measurement cycle for only a few devices can take several days. In this work, we demonstrate wafer-scale cryogenic characterization of a recently developed TiW/Al-AlOx/TiW normal-metal tunnel junction technology using CBTs. Measurements performed in a 300 mm cryogenic wafer prober (CWP) show on-chip electron temperatures below 700 mK across a full 150 mm wafer, as determined by primary thermometry. These results establish wafer-level testing below 1 K as a viable approach for large-scale cryogenic characterization of electrical devices, opening a pathway toward high-throughput screening of quantum devices and direct wafer-scale characterization of aluminum-based superconducting circuits.
We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. The minimum feature size of resistors and inductors in the process is 250 nm. We present data on the mutual inductance of Nb stripline and microstrip inductors with linewidth and spacing from 250 nm to 1 μm made on the same or adjacent Nb layers, as well as the data on the linewidth and resistance uniformity.