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arXiv:1704.07683 · IEEE International Superconductive Electronics Conference (ISEC)

Developments toward a 250-nm, Fully Planarized Fabrication Process with Ten Superconducting Layers and Self-Shunted Josephson Junctions

Sergey K. Tolpygo, Vladimir Bolkhovsky, Ravi Rastogi, Scott Zarr, Alexandra L. Day, Terence J. Weir, Alex Wynn, L. M. Johnson

Published Jun 1, 2017• 15 citations
arXivHTMLPDF

Abstract

We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. The minimum feature size of resistors and inductors in the process is 250 nm. We present data on the mutual inductance of Nb stripline and microstrip inductors with linewidth and spacing from 250 nm to 1 μm made on the same or adjacent Nb layers, as well as the data on the linewidth and resistance uniformity.

DOI
10.1109/isec.2017.8314189

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Data are presented on mutual and self-inductance of various inductors used in multilayered superconductor integrated circuits: microstrips and striplines with widths from 250 nm to a few micrometers, located on the same layer at various distances from each other, from 250 nm to a few micrometers, and/or on different layers spaced vertically; effect of long slits in the ground plane(s) along the inductors on their mutual inductance; inductance of right-angled bends; and inductance of meanders. Measurements were done using circuits fabricated in the SFQ5ee and the SC1 fully planarized fabrication processes with eight niobium layers and Nb/Al-AlOx/Nb Josephson junctions, developed at MIT Lincoln Laboratory for superconductor electronics. Simple analytical expressions for mutual and self-inductance of the basic inductors are given, describing experimental data with accuracy better than 2% over a very wide range of parameters. Mutual coupling between microstrips is long-ranged and decreases as a second power of distance between them, making microstrips unsuitable for very large scale integrated circuits. Mutual inductance of striplines decreases exponentially with distance between them on a scale of$({\boldsymbol{H}} + 2{\boldsymbol{\lambda }})/{\boldsymbol{\pi }}$∼ 0.3 μm, where${\boldsymbol{H}}$and${\boldsymbol{\lambda }}$are, respectively, the distance between and magnetic field penetration depth in superconducting ground planes, whereas superconducting properties of the signal traces are practically irrelevant. This decay distance determines the scale of integration above which adjacent inductors in a circuit become strongly coupled. Dependence of mutual inductance on the linewidth of wires is weak. As a result, the area of flux transformers—an essential component of all superconductor digital circuits using ac power, qubits, and sensor arrays—scales poorly with the linewidth, potentially restricting scalability of the circuits.

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We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. The minimum feature size of resistors and inductors in the process is 250 nm. We present data on the mutual inductance of Nb stripline and microstrip inductors with linewidth and spacing from 250 nm to 1 μm made on the same or adjacent Nb layers, as well as the data on the linewidth and resistance uniformity.
Abstract Data are presented on the inductance of various features used in superconductor digital integrated circuits: microstrip and stripline inductors with linewidths down to 120 nm and different combinations of ground plane layers, effect of perforations of various sizes in the ground planes and their distance to the inductors on inductance, inductance of vias of various sizes between adjacent layers, inductance of composite vias between distant superconducting layers. Test circuits used for the measurements were fabricated in a new 150 nm node of a fully planarized process with eight niobium layers developed at MIT Lincoln Laboratory for superconductor electronics as well as in our standard SFQ5ee and SC1 fabrication processes with 250 nm minimum feature size. The new SC2 process utilizes 193 nm photolithography in combination with plasma etching and chemical mechanical planarization of interlayer dielectrics to define inductors with linewidth down to about 100 nm on critical layers. The standard processes use 248 nm photolithography. The measured data are compared with the results of inductance extraction using software packages InductEx and wxLC. Variations of circuit inductors caused by the fabrication processes are discussed. Magnetic flux trapping in ground plane moats and its coupling to nearby inductors are discussed for circuit cooling in a residual field of several configurations.
To increase the integration scale of superconductor electronics, we are developing a new node, titled SFQ7ee, of the fabrication process at MIT Lincoln Laboratory. In comparison to the existing SFQ5ee node, we increased the number of fully planarized superconducting layers to ten and utilized NbN and NbN/Nb kinetic inductors to increase the possible inductor number density above a hundred million inductors per cm2. Increasing the Josephson junction number density to the same level requires implementing self-shunted high-JcJosephson junctions. We investigated the properties of Nb/NbNx/Nb trilayer junctions as a potential replacement of high-JcNb/Al-AlOx/Nb junctions, where NbNxis a disordered, overstoichiometric, nonsuperconducting nitride deposited by reactive sputtering. Dependences of theIcRnproduct and Josephson critical current density, Jc on the NbNx barrier thickness and temperature were studied in the thickness range from 5 nm to 20 nm. The fabricated junctions can be well described by the microscopic theory of SNS junctions, assuming no suppression of the energy gap in Nb electrodes near the NbNxinterfaces and a Cooper pair decay length in the NbNx barrier, ξnTcof about 2.3 nm. Current-voltage characteristics of the junctions are well described by the resistively and capacitively shunted junction (RCSJ) model without excess current. In the studied rangeJc2, the Nb/NbNx/Nb junctions have lower values of the specific resistanceRnA, lower IcRn products, and a stronger dependence of theIcRnon temperature than the self-shunted or critically damped externally shunted Nb/Al-AlOx/Nb junctions with the same critical current density; A is the junction area,Icthe junction critical current, and Rnthe effective shunting resistance.
Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90° bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. It has been found that the inductance per unit length of stripline and microstrip line inductors continues to grow as the inductor linewidth is reduced deep into the submicron range to the widths comparable to the film thickness and magnetic field penetration depth. It is shown that the linewidth reduction does not lead to widening of the parameter spread due to diminishing sensitivity of the inductance to the linewidth and dielectric thickness. The experimental results were compared with numeric inductance extraction using commercial software and freeware, and a good agreement was found for 3-D inductance extractors. Methods of further miniaturization of circuit inductors for achieving circuit densities> 106Josephson junctions per cm2are discussed.
We present measurements of the self- and mutual inductance of NbN and NbN/Nb bilayer inductors (microstrips, striplines, serpentines, etc.) with Nb ground plane(s) fabricated in an advanced process for superconductor electronics developed at MIT Lincoln Laboratory. In this process, the signal traces of logic cell inductors are made either of a 200-nm NbN layer with${{\bm{T}}}_{\bm{c}} \approx 15.5Koranin−situdepositedNbN/Nbbilayer,replacinga200−nmNblayerM6inthestandardSFQ5eeprocesswithninesuperconductinglayerson200−mmwafers.Nbgroundplanesarepreservedtomaintainahighlevelofinterlayershieldingandlowintralayermutualcoupling.Atwo−steppatterningofthetopNbandthebottomNbNlayersoftheNbN/Nbbilayerallowsthecreationofinductorswithaverywiderangeofinductances,fromlowvalues∼0.4pH/μmtypicalforNbgeometricalinductorsto∼35pH/μmtypicalforthin−filmkineticinductors.ThemutualinductanceofvariouscombinationsofNbN,Nb,andNbN/Nbinductorsdoesnotdependonsuperconductingpropertiesofthesignaltracesinthestudiedrangeoflinewidths,15.5 K or an in-situ deposited NbN/Nb bilayer, replacing a 200-nm Nb layer M6 in the standard SFQ5ee process with nine superconducting layers on 200-mm wafers. Nb ground planes are preserved to maintain a high level of interlayer shielding and low intralayer mutual coupling. A two-step patterning of the top Nb and the bottom NbN layers of the NbN/Nb bilayer allows the creation of inductors with a very wide range of inductances, from low values ∼0.4 pH/μm typical for Nb geometrical inductors to ∼35 pH/μm typical for thin-film kinetic inductors. The mutual inductance of various combinations of NbN, Nb, and NbN/Nb inductors does not depend on superconducting properties of the signal traces in the studied range of linewidths,15.5Koranin−situdepositedNbN/Nbbilayer,replacinga200−nmNblayerM6inthestandardSFQ5eeprocesswithninesuperconductinglayerson200−mmwafers.Nbgroundplanesarepreservedtomaintainahighlevelofinterlayershieldingandlowintralayermutualcoupling.Atwo−steppatterningofthetopNbandthebottomNbNlayersoftheNbN/Nbbilayerallowsthecreationofinductorswithaverywiderangeofinductances,fromlowvalues∼0.4pH/μmtypicalforNbgeometricalinductorsto∼35pH/μmtypicalforthin−filmkineticinductors.ThemutualinductanceofvariouscombinationsofNbN,Nb,andNbN/Nbinductorsdoesnotdependonsuperconductingpropertiesofthesignaltracesinthestudiedrangeoflinewidths,{\bm{w}};itequalsthemutualinductanceoftheNbinductorswiththeequivalentgeometryandplacementbetweenthegroundplanes.ThemeasuredmagneticfieldpenetrationdepthinNbNfilmsdepositedbyreactivesputteringat200°CisλNbN=491±5nm.Themeasuredkineticinductanceofthefilmswiththicknesses; it equals the mutual inductance of the Nb inductors with the equivalent geometry and placement between the ground planes. The measured magnetic field penetration depth in NbN films deposited by reactive sputtering at 200 °C isλNbN= 491 ± 5 nm. The measured kinetic inductance of the films with thicknesses;itequalsthemutualinductanceoftheNbinductorswiththeequivalentgeometryandplacementbetweenthegroundplanes.ThemeasuredmagneticfieldpenetrationdepthinNbNfilmsdepositedbyreactivesputteringat200°CisλNbN=491±5nm.Themeasuredkineticinductanceofthefilmswiththicknesses{\bm{t}}\ = {\bm{\ }}200nmand150nm,respectively1.51pH/sqand2.06pH/sq,islargerthanthatexpectedforconventionalsuperconductorswithshortmeanfreepath,correspondingtoabout25200 nm and 150 nm, respectively 1.51 pH/sq and 2.06 pH/sq, is larger than that expected for conventional superconductors with short mean free path, corresponding to about 25% lower superfluid density. We also measured kinetic inductance of the right-angle bends of NbN striplines and found it to be negligible at200nmand150nm,respectively1.51pH/sqand2.06pH/sq,islargerthanthatexpectedforconventionalsuperconductorswithshortmeanfreepath,correspondingtoabout25{\bm{w}} < {\bm{\lambda }}_{{\bm{NbN}}}^2/{\bm{t}}$, indicating an insignificant effect of current crowding in the presence of superconducting ground plane(s). Implementing NbN and NbN/Nb kinetic inductors enables a significant increase in the integration scale of superconductor digital electronics.
We report on technique and results for superconductor electronics fabrication process, featuring customizable number of planarized superconducting layers. The novel technique enhanced yield on stackable vias of our standard planarized process (RIPPLE) by eliminating the need for an additional deposition of aluminum as an etch stop in the metal-via stack. The drawback of the previous approach was the difficulty in processing aluminum using either wet or dry etch mechanisms. Here, we discuss details of the novel fabrication process flow and its realization for 4.5 kA/cm2 fabrication process with six Nb layers with two fully planarized layers. We report test results of various planarization diagnostics structures, accounting the influence of topology on Josephson junction quality, as well as yield and critical current of via stacks. We also report on inductance measurement results providing information on interlayer dielectric thickness for planarized layers; confirming a good uniformity over the wafer. Basic components of superconducting logic such as dc/SFQ, SFQ/dc converters, Josephson transmission lines (JTLs), and simple digital circuits such as half-adder (HA) have been designed, fabricated and tested using either conventional (RSFQ) or energy-efficient (ERSFQ) approach. The ERSFQ HA cells with bias inductors fabricated in two planarized layers were shown to function with the operational margins of +/-22%.
Data are presented on mutual and self-inductance of various inductors used in multilayered superconductor integrated circuits: microstrips and striplines with widths from 250 nm to a few micrometers, located on the same layer at various distances from each other, from 250 nm to a few micrometers, and/or on different layers spaced vertically; effect of long slits in the ground plane(s) along the inductors on their mutual inductance; inductance of right-angled bends; and inductance of meanders. Measurements were done using circuits fabricated in the SFQ5ee and the SC1 fully planarized fabrication processes with eight niobium layers and Nb/Al-AlOx/Nb Josephson junctions, developed at MIT Lincoln Laboratory for superconductor electronics. Simple analytical expressions for mutual and self-inductance of the basic inductors are given, describing experimental data with accuracy better than 2% over a very wide range of parameters. Mutual coupling between microstrips is long-ranged and decreases as a second power of distance between them, making microstrips unsuitable for very large scale integrated circuits. Mutual inductance of striplines decreases exponentially with distance between them on a scale of(H+2λ)/π({\boldsymbol{H}} + 2{\boldsymbol{\lambda }})/{\boldsymbol{\pi }}(H+2λ)/π∼ 0.3 μm, whereH{\boldsymbol{H}}Handλ{\boldsymbol{\lambda }}λare, respectively, the distance between and magnetic field penetration depth in superconducting ground planes, whereas superconducting properties of the signal traces are practically irrelevant. This decay distance determines the scale of integration above which adjacent inductors in a circuit become strongly coupled. Dependence of mutual inductance on the linewidth of wires is weak. As a result, the area of flux transformers—an essential component of all superconductor digital circuits using ac power, qubits, and sensor arrays—scales poorly with the linewidth, potentially restricting scalability of the circuits.