Abstract Data are presented on the inductance of various features used in superconductor digital integrated circuits: microstrip and stripline inductors with linewidths down to 120 nm and different combinations of ground plane layers, effect of perforations of various sizes in the ground planes and their distance to the inductors on inductance, inductance of vias of various sizes between adjacent layers, inductance of composite vias between distant superconducting layers. Test circuits used for the measurements were fabricated in a new 150 nm node of a fully planarized process with eight niobium layers developed at MIT Lincoln Laboratory for superconductor electronics as well as in our standard SFQ5ee and SC1 fabrication processes with 250 nm minimum feature size. The new SC2 process utilizes 193 nm photolithography in combination with plasma etching and chemical mechanical planarization of interlayer dielectrics to define inductors with linewidth down to about 100 nm on critical layers. The standard processes use 248 nm photolithography. The measured data are compared with the results of inductance extraction using software packages InductEx and wxLC. Variations of circuit inductors caused by the fabrication processes are discussed. Magnetic flux trapping in ground plane moats and its coupling to nearby inductors are discussed for circuit cooling in a residual field of several configurations.
Abstract Data are presented on the inductance of various features used in superconductor digital integrated circuits: microstrip and stripline inductors with linewidths down to 120 nm and different combinations of ground plane layers, effect of perforations of various sizes in the ground planes and their distance to the inductors on inductance, inductance of vias of various sizes between adjacent layers, inductance of composite vias between distant superconducting layers. Test circuits used for the measurements were fabricated in a new 150 nm node of a fully planarized process with eight niobium layers developed at MIT Lincoln Laboratory for superconductor electronics as well as in our standard SFQ5ee and SC1 fabrication processes with 250 nm minimum feature size. The new SC2 process utilizes 193 nm photolithography in combination with plasma etching and chemical mechanical planarization of interlayer dielectrics to define inductors with linewidth down to about 100 nm on critical layers. The standard processes use 248 nm photolithography. The measured data are compared with the results of inductance extraction using software packages InductEx and wxLC. Variations of circuit inductors caused by the fabrication processes are discussed. Magnetic flux trapping in ground plane moats and its coupling to nearby inductors are discussed for circuit cooling in a residual field of several configurations.
Data are presented on mutual and self-inductance of various inductors used in multilayered superconductor integrated circuits: microstrips and striplines with widths from 250 nm to a few micrometers, located on the same layer at various distances from each other, from 250 nm to a few micrometers, and/or on different layers spaced vertically; effect of long slits in the ground plane(s) along the inductors on their mutual inductance; inductance of right-angled bends; and inductance of meanders. Measurements were done using circuits fabricated in the SFQ5ee and the SC1 fully planarized fabrication processes with eight niobium layers and Nb/Al-AlOx/Nb Josephson junctions, developed at MIT Lincoln Laboratory for superconductor electronics. Simple analytical expressions for mutual and self-inductance of the basic inductors are given, describing experimental data with accuracy better than 2% over a very wide range of parameters. Mutual coupling between microstrips is long-ranged and decreases as a second power of distance between them, making microstrips unsuitable for very large scale integrated circuits. Mutual inductance of striplines decreases exponentially with distance between them on a scale of(H+2λ)/π∼ 0.3 μm, whereHandλare, respectively, the distance between and magnetic field penetration depth in superconducting ground planes, whereas superconducting properties of the signal traces are practically irrelevant. This decay distance determines the scale of integration above which adjacent inductors in a circuit become strongly coupled. Dependence of mutual inductance on the linewidth of wires is weak. As a result, the area of flux transformers—an essential component of all superconductor digital circuits using ac power, qubits, and sensor arrays—scales poorly with the linewidth, potentially restricting scalability of the circuits.
Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90° bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. It has been found that the inductance per unit length of stripline and microstrip line inductors continues to grow as the inductor linewidth is reduced deep into the submicron range to the widths comparable to the film thickness and magnetic field penetration depth. It is shown that the linewidth reduction does not lead to widening of the parameter spread due to diminishing sensitivity of the inductance to the linewidth and dielectric thickness. The experimental results were compared with numeric inductance extraction using commercial software and freeware, and a good agreement was found for 3-D inductance extractors. Methods of further miniaturization of circuit inductors for achieving circuit densities> 106Josephson junctions per cm2are discussed.
We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. The minimum feature size of resistors and inductors in the process is 250 nm. We present data on the mutual inductance of Nb stripline and microstrip inductors with linewidth and spacing from 250 nm to 1 μm made on the same or adjacent Nb layers, as well as the data on the linewidth and resistance uniformity.
We present measurements of the self- and mutual inductance of NbN and NbN/Nb bilayer inductors (microstrips, striplines, serpentines, etc.) with Nb ground plane(s) fabricated in an advanced process for superconductor electronics developed at MIT Lincoln Laboratory. In this process, the signal traces of logic cell inductors are made either of a 200-nm NbN layer with${{\bm{T}}}_{\bm{c}} \approx 15.5Koranin−situdepositedNbN/Nbbilayer,replacinga200−nmNblayerM6inthestandardSFQ5eeprocesswithninesuperconductinglayerson200−mmwafers.Nbgroundplanesarepreservedtomaintainahighlevelofinterlayershieldingandlowintralayermutualcoupling.Atwo−steppatterningofthetopNbandthebottomNbNlayersoftheNbN/Nbbilayerallowsthecreationofinductorswithaverywiderangeofinductances,fromlowvalues∼0.4pH/μmtypicalforNbgeometricalinductorsto∼35pH/μmtypicalforthin−filmkineticinductors.ThemutualinductanceofvariouscombinationsofNbN,Nb,andNbN/Nbinductorsdoesnotdependonsuperconductingpropertiesofthesignaltracesinthestudiedrangeoflinewidths,{\bm{w}};itequalsthemutualinductanceoftheNbinductorswiththeequivalentgeometryandplacementbetweenthegroundplanes.ThemeasuredmagneticfieldpenetrationdepthinNbNfilmsdepositedbyreactivesputteringat200°CisλNbN=491±5nm.Themeasuredkineticinductanceofthefilmswiththicknesses{\bm{t}}\ = {\bm{\ }}200nmand150nm,respectively1.51pH/sqand2.06pH/sq,islargerthanthatexpectedforconventionalsuperconductorswithshortmeanfreepath,correspondingtoabout25{\bm{w}} < {\bm{\lambda }}_{{\bm{NbN}}}^2/{\bm{t}}$, indicating an insignificant effect of current crowding in the presence of superconducting ground plane(s). Implementing NbN and NbN/Nb kinetic inductors enables a significant increase in the integration scale of superconductor digital electronics.
Flux transformers are the necessary component of all superconductor digital integrated circuits utilizing flux biasing and ac power excitation and clocking of logic cells, e.g., adiabatic quantum flux parametron (AQFP), reciprocal quantum logic (RQL), superconducting sensor arrays, qubits, etc. On average, one transformer is required per one Josephson junction. We consider limitations to the integration scale (device number density) imposed by the critical current of the ac power transmission lines (primary of the transformers) and cross-coupling between the adjacent transformers. The former sets the minimum linewidth and the mutual coupling length in the transformer, whereas the latter sets the minimum spacing between the transformers. Decreasing linewidth of superconducting (Nb) wires increases kinetic inductance of the transformer's secondary, decreasing its length and mutual coupling to the primary. This limits the minimum size. As a result, there is a minimum linewidth${{\boldsymbol{w}}}_{\mathbf{min}}\sim $100 nm, which determines the maximum achievable scale of integration. Using AQFP circuits as an example, we calculate dependences of the AQFP number density on linewidth for various types of microstrip-based and stripline-based transformers and inductors available in the SFQ5ee fabrication process developed at MIT Lincoln Laboratory, and estimate the maximum circuit density as a few million AQFPs per cm2. We propose an advanced fabrication process for a 10× increase in the density of AQFP and other ac-powered circuits. In this process, inductors are formed from a patterned bilayer of a geometrical inductance material, Nb, deposited over a layer of high kinetic inductance material, e.g., NbN. Individual pattering of the bilayer layers allows to create stripline inductors in a wide range of inductances, from the low values typical to Nb striplines to the high values typical for NbN thin films, and preserve sufficient mutual coupling in stripline transformers with extremely low cross-talk. Energy efficiency of ac-powered circuits is limited by dielectric losses in the ac power transmissions lines. Problems of scaling associated with multiphase ac power distribution are discussed.
Using a fully automated cryogenic wafer prober, we measured superconductor fabrication process control monitors and simple integrated circuits on 200 mm wafers at 4.2 K, including Nb/Al-AlOx/Nb Josephson junctions, SQUID-based circuits for measuring inductors, test structures for measuring critical current of superconducting wires and vias, resistors, etc., to demonstrate the feasibility of using the system for characterizing niobium superconducting devices and integrated circuits on a wafer scale. The data on the wafer-scale distributions of the junction tunnel resistance, energy gap, inductance of Nb layers, critical currents of interlayer vias are presented. The wafers were fabricated in the SFQ5ee process, the fully planarized process with eight niobium layers and a layer of kinetic inductors, developed for superconductor electronics at MIT Lincoln Laboratory. The cryogenic wafer prober was developed at HPD/ FormFactor, Inc.