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arXiv:2210.02632 · IEEE Transactions on Applied Superconductivity

Scalability of Superconductor Electronics: Limitations Imposed by AC Clock and Flux Bias Transformers

Sergey K. Tolpygo

Published Dec 19, 2022• 11 citations
arXivHTMLPDF

Abstract

Flux transformers are the necessary component of all superconductor digital integrated circuits utilizing flux biasing and ac power excitation and clocking of logic cells, e.g., adiabatic quantum flux parametron (AQFP), reciprocal quantum logic (RQL), superconducting sensor arrays, qubits, etc. On average, one transformer is required per one Josephson junction. We consider limitations to the integration scale (device number density) imposed by the critical current of the ac power transmission lines (primary of the transformers) and cross-coupling between the adjacent transformers. The former sets the minimum linewidth and the mutual coupling length in the transformer, whereas the latter sets the minimum spacing between the transformers. Decreasing linewidth of superconducting (Nb) wires increases kinetic inductance of the transformer's secondary, decreasing its length and mutual coupling to the primary. This limits the minimum size. As a result, there is a minimum linewidth${{\boldsymbol{w}}}_{\mathbf{min}}\sim $100 nm, which determines the maximum achievable scale of integration. Using AQFP circuits as an example, we calculate dependences of the AQFP number density on linewidth for various types of microstrip-based and stripline-based transformers and inductors available in the SFQ5ee fabrication process developed at MIT Lincoln Laboratory, and estimate the maximum circuit density as a few million AQFPs per cm2. We propose an advanced fabrication process for a 10× increase in the density of AQFP and other ac-powered circuits. In this process, inductors are formed from a patterned bilayer of a geometrical inductance material, Nb, deposited over a layer of high kinetic inductance material, e.g., NbN. Individual pattering of the bilayer layers allows to create stripline inductors in a wide range of inductances, from the low values typical to Nb striplines to the high values typical for NbN thin films, and preserve sufficient mutual coupling in stripline transformers with extremely low cross-talk. Energy efficiency of ac-powered circuits is limited by dielectric losses in the ac power transmissions lines. Problems of scaling associated with multiphase ac power distribution are discussed.

DOI
10.1109/tasc.2022.3230373

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Abstract Superconductor logic families can operate with small power dissipation and are thus suitable as building blocks for various computing systems. In some applications, superconductor logic circuits should be designed using Josephson junctions with low I c values ( I c : critical current). For instance, lowering I c values enables qubit interface circuits to operate with very small power dissipation at ~10 mK and stochastic electronics to easily induce stochastic operations. In this study, we develop the AIST 1 kA cm −2 Nb planarized process (1KP) with a minimum critical current of 10 µA, dedicated to the design of qubit interface circuits and stochastic electronics. We also develop rapid single-flux-quantum (RSFQ) and adiabatic quantum-flux-parametron (AQFP) cell libraries using the 1KP. The power dissipation of RSFQ logic using the 1KP can be reduced to 3.2% of that for conventional RSFQ logic by reducing both I c values and a bias voltage. Furthermore, the amount of supply currents for AQFP circuits using the 1KP can be reduced to ~40% of that for conventional AQFP circuits due to a large mutual inductance between AQFP gates and excitation lines, which results from a reduction in I c and an increase in inductances. We demonstrate RSFQ and AQFP circuits fabricated by the 1KP at 4.2 K. These results indicate that RSFQ and AQFP circuits using the 1KP have the potential to be used for the design of qubit interface circuits and stochastic electronics.
Data are presented on mutual and self-inductance of various inductors used in multilayered superconductor integrated circuits: microstrips and striplines with widths from 250 nm to a few micrometers, located on the same layer at various distances from each other, from 250 nm to a few micrometers, and/or on different layers spaced vertically; effect of long slits in the ground plane(s) along the inductors on their mutual inductance; inductance of right-angled bends; and inductance of meanders. Measurements were done using circuits fabricated in the SFQ5ee and the SC1 fully planarized fabrication processes with eight niobium layers and Nb/Al-AlOx/Nb Josephson junctions, developed at MIT Lincoln Laboratory for superconductor electronics. Simple analytical expressions for mutual and self-inductance of the basic inductors are given, describing experimental data with accuracy better than 2% over a very wide range of parameters. Mutual coupling between microstrips is long-ranged and decreases as a second power of distance between them, making microstrips unsuitable for very large scale integrated circuits. Mutual inductance of striplines decreases exponentially with distance between them on a scale of(H+2λ)/π({\boldsymbol{H}} + 2{\boldsymbol{\lambda }})/{\boldsymbol{\pi }}(H+2λ)/π∼ 0.3 μm, whereH{\boldsymbol{H}}Handλ{\boldsymbol{\lambda }}λare, respectively, the distance between and magnetic field penetration depth in superconducting ground planes, whereas superconducting properties of the signal traces are practically irrelevant. This decay distance determines the scale of integration above which adjacent inductors in a circuit become strongly coupled. Dependence of mutual inductance on the linewidth of wires is weak. As a result, the area of flux transformers—an essential component of all superconductor digital circuits using ac power, qubits, and sensor arrays—scales poorly with the linewidth, potentially restricting scalability of the circuits.
Abstract Data are presented on the inductance of various features used in superconductor digital integrated circuits: microstrip and stripline inductors with linewidths down to 120 nm and different combinations of ground plane layers, effect of perforations of various sizes in the ground planes and their distance to the inductors on inductance, inductance of vias of various sizes between adjacent layers, inductance of composite vias between distant superconducting layers. Test circuits used for the measurements were fabricated in a new 150 nm node of a fully planarized process with eight niobium layers developed at MIT Lincoln Laboratory for superconductor electronics as well as in our standard SFQ5ee and SC1 fabrication processes with 250 nm minimum feature size. The new SC2 process utilizes 193 nm photolithography in combination with plasma etching and chemical mechanical planarization of interlayer dielectrics to define inductors with linewidth down to about 100 nm on critical layers. The standard processes use 248 nm photolithography. The measured data are compared with the results of inductance extraction using software packages InductEx and wxLC. Variations of circuit inductors caused by the fabrication processes are discussed. Magnetic flux trapping in ground plane moats and its coupling to nearby inductors are discussed for circuit cooling in a residual field of several configurations.
Abstract We review the existing fabrication processes for superconductor digital electronics and describe approaches to increasing the scale of integration of superconducting digital circuits from the current level of about one million Josephson junctions (JJs) on a 1-cm 2 chip toward ten million JJs per chip. We present designs of ac-clocked Single Flux Quantum (SFQ) shift registers, convenient benchmarking circuits, in a 250-nm-linewidth superconductor electronics fabrication process developed recently at MIT Lincoln Laboratory (MIT LL). For shift registers using resistively shunted JJs with Josephson critical current density, J c of 100 μA/μm 2 , we achieved a record-high circuit density of 4.2·10 6 JJs per cm 2 , a factor of three higher than the previous record obtained in the MIT LL 350-nm-linewidth SFQ5ee process. Using self-shunted JJs with J c of 600 μA/μm 2 , we increased this record circuit density to 7.4·10 6 JJs per cm 2 .
Adiabatic quantum-flux-parametron (AQFP) superconductor logic is a proven energy-efficient digital technology for various applications. To address the scalability challenges of this technology, we investigated AQFP shift registers with the AQFP footprint area reduced by 25% with respect to prior work and with the >2× denser overall circuit designs obtained by eliminating the previously used free space between the AQFPs. We also investigated AQFP cells with different designs of flux trapping moats in the superconducting ground plane as well as compact AQFP cells that took advantage of the smaller feature sizes available in the new fabrication process, SFQ5ee+, at MIT Lincoln Laboratory (MIT LL). This new process features nine planarized Nb layers with a 0.25 μm minimum linewidth. The fabricated circuits were tested in a liquid He immersion probe and a commercial closed-cycle cryocooler using a controlled cooling rate through the superconducting critical temperature,Tc. Using multiple thermal cycles, we investigated flux trapping in the dense AQFP shift registers as well as in the registers using the old (sparse) AQFP designs at two levels of the residual magnetic field, about 0.53 μT and about 1.2 μT. The sparse designs demonstrated 95% to almost 100% probability of operation after the cooldown and very wide operation margins, although the flux trapping probability was increasing with circuit complexities. The margins were similarly wide in the newer dense designs, but flux trapping probability that rendered the registers nonoperational was significantly, by an order of magnitude, higher in these denser circuits and was also very sensitive to the moats' shape and location. Our findings indicate that AQFP circuits are amendable to increasing the scale of integration and further densification, but a careful moat design and optimization are required to reduce flux trapping effects in the dense AQFP circuits.