Adiabatic quantum-flux-parametron (AQFP) superconductor logic is a proven energy-efficient digital technology for various applications. To address the scalability challenges of this technology, we investigated AQFP shift registers with the AQFP footprint area reduced by 25% with respect to prior work and with the >2× denser overall circuit designs obtained by eliminating the previously used free space between the AQFPs. We also investigated AQFP cells with different designs of flux trapping moats in the superconducting ground plane as well as compact AQFP cells that took advantage of the smaller feature sizes available in the new fabrication process, SFQ5ee+, at MIT Lincoln Laboratory (MIT LL). This new process features nine planarized Nb layers with a 0.25 μm minimum linewidth. The fabricated circuits were tested in a liquid He immersion probe and a commercial closed-cycle cryocooler using a controlled cooling rate through the superconducting critical temperature,Tc. Using multiple thermal cycles, we investigated flux trapping in the dense AQFP shift registers as well as in the registers using the old (sparse) AQFP designs at two levels of the residual magnetic field, about 0.53 μT and about 1.2 μT. The sparse designs demonstrated 95% to almost 100% probability of operation after the cooldown and very wide operation margins, although the flux trapping probability was increasing with circuit complexities. The margins were similarly wide in the newer dense designs, but flux trapping probability that rendered the registers nonoperational was significantly, by an order of magnitude, higher in these denser circuits and was also very sensitive to the moats' shape and location. Our findings indicate that AQFP circuits are amendable to increasing the scale of integration and further densification, but a careful moat design and optimization are required to reduce flux trapping effects in the dense AQFP circuits.
Adiabatic quantum-flux-parametron (AQFP) superconductor logic is a proven energy-efficient digital technology for various applications. To address the scalability challenges of this technology, we investigated AQFP shift registers with the AQFP footprint area reduced by 25% with respect to prior work and with the >2× denser overall circuit designs obtained by eliminating the previously used free space between the AQFPs. We also investigated AQFP cells with different designs of flux trapping moats in the superconducting ground plane as well as compact AQFP cells that took advantage of the smaller feature sizes available in the new fabrication process, SFQ5ee+, at MIT Lincoln Laboratory (MIT LL). This new process features nine planarized Nb layers with a 0.25 μm minimum linewidth. The fabricated circuits were tested in a liquid He immersion probe and a commercial closed-cycle cryocooler using a controlled cooling rate through the superconducting critical temperature,Tc. Using multiple thermal cycles, we investigated flux trapping in the dense AQFP shift registers as well as in the registers using the old (sparse) AQFP designs at two levels of the residual magnetic field, about 0.53 μT and about 1.2 μT. The sparse designs demonstrated 95% to almost 100% probability of operation after the cooldown and very wide operation margins, although the flux trapping probability was increasing with circuit complexities. The margins were similarly wide in the newer dense designs, but flux trapping probability that rendered the registers nonoperational was significantly, by an order of magnitude, higher in these denser circuits and was also very sensitive to the moats' shape and location. Our findings indicate that AQFP circuits are amendable to increasing the scale of integration and further densification, but a careful moat design and optimization are required to reduce flux trapping effects in the dense AQFP circuits.
Abstract Adiabatic quantum-flux-parametron (AQFP) is an adiabatic logic based on the quantum-flux-parametron. It has extremely low switching energy, as well as high signal gain and high robustness. In this work, we present the development of an AQFP cell library using the MIT LL 100 μ A μ m −2 superconductor electronics fabrication process, SFQ5ee. Four types of basic sub-cells, i.e. buffer, inverter, constant, and branch, are designed as the building blocks for combinational AQFP logic cells. Taking advantage of the 8 metal layers, we place the dc superconducting quantum interference device (SQUID) part of a buffer above the ground plane and the signal transformer part below the ground plane to mitigate unwanted couplings. In addition, by vertically overlapping the signal transformer and the dc SQUID, the dimension of a buffer is reduced to 15 μ m × 20 μ m, which is only 30% of that of the conventional design. More complex AQFP logic cells, such as the majority gate, AND gate, and OR gate, are designed by arraying the sub-cells together. Correct operations and wide excitation current margins are confirmed for the established AQFP logic cells by both simulation and experiments.
A variety of superconductor integrated circuits composed of six ac-powered SFQ shift registers with a total of 27078 bits and 108500 Josephson junctions (JJs) per 5 mm × 5 mm chip have been designed, fabricated, and tested to characterize flux trapping, fabrication process yield, and parameter spread. The six 4513-bit registers in the circuits have a common single-phase ac clock and individual input/output drivers, allowing for their parallel testing. We have investigated flux trapping in the circuits with various geometry, size, distance between moats in active ground planes (GPs), and containing up to three additional ‘dummy’ GPs, using multiple cooldowns through the critical temperature with various cooling rates and residual magnetic fields up to ∼ 1.2 µT. For the slit-type and square moats arrayed along the sides of the register cells, we have found a negligible effect of flux sequestered in the moats on the operating margins of the registers, and a negligible probability of detrimental flux trapping outside of the moats. Circuits with 0.3-µm-wide slit moats occupying less than 2% of the circuit area were fully operational in 100% of cooldowns, supporting the viability of a very large-scale integration of superconductor digital circuits. We have also found a strong enhancement of flux trapping outside the moats in circuits with closely spaced GPs and determined a critical distance,${{{\boldsymbol{t}}}_{\boldsymbol{c}}} \approx $0.6 µm, between them. The presence of two or more GPs spaced below thetcrendered the circuits nonoperational in 100% of cooldowns. We have measured 30 chips with over 3M JJs and determined individual cell operating margins in 138 registers to characterize the fabrication-related parameter spread and detect fabrication defects and flux-trapping events. By finding outlier bit-cells in the statistical distribution of the individual cell margins, we detected about one fabrication defect per million JJs, in most cases causing magnetic flux trapping in the affected cell.The circuits have been fabricated in the SFQ5ee fabrication process at MIT Lincoln Laboratory (MIT LL).
Adiabatic quantum-flux-parametron (AQFP) is an ac-biased logic family noted for its extremely low switching energy of around 1.4 zJ per Josephson junction (JJ) at a clock frequency of 5 GHz. Therefore, the AQFP logic family provides a high-speed, ultra-low-energy alternative to CMOS technology. However, quantised flux, such as vortices, trapped in the superconductor film can adversely affect circuit operation. A conventional solution to vortices is the introduction of low potential holes, also known as moats, within the film. Although basic guidelines have been introduced from published circuits, there is currently no standard method for designing and analysing moats for AQFP circuits. The double gate process (DGP) is a double-active-layered niobium fabrication process that allows for more compact circuits. But the effects of quantised flux for AQFP circuits on both active layers are currently unknown. We use 3D parameter extraction software tools to analyse the effect of various moat structures for AQFP logic cells for DGP and improve layout and moat placement designs.
We develop an ac-biased shift register introduced in our previous work (V. K. Semenov et al., IEEE Trans. Appl. Supercond., vol. 25, no. 3, 1301507, June 2015) into a benchmark circuit for evaluation of superconductor electronics fabrication technology. The developed testing technique allows for extracting margins of all individual cells in the shift register, which in turn makes it possible to estimate statistical distribution of Josephson junctions (JJs) in the circuit. We applied this approach to successfully test registers having 8-, 16-, 36-, and 202 thousand cells and, respectively, about 33-, 65-, 144-, and 809 thousand JJs. The circuits were fabricated at MIT Lincoln Laboratory, using a fully planarized process, 0.4-μm inductor linewidth and 1.33 × 106cm-2junction density. They are presently the largest operational superconducting SFQ circuits ever made. The developed technique distinguishes between “hard” defects (fabrication-related) and “soft” defects (measurement-related) and locates them in the circuit. The “soft” defects are specific to superconducting circuits and caused by magnetic flux trapping either inside the active cells or in the dedicated flux-trapping moats near the cells. The number and distribution of “soft” defects depend on the ambient magnetic field and vary with thermal cycling even if done in the same magnetic environment.
We have been developing the adiabatic quantum-flux-parametron (AQFP), which is an ultra-low-power superconductor logic family. To date, somewhat large AQFP circuits, such as a 4-bit microprocessor and an 8-bit adder, have been demonstrated. To design much larger devices, space-efficient logic circuits are needed. Therefore, in a previous study, we proposed the directly coupled quantum-flux-parametron (DQFP). DQFP circuits propagate data via a direct connection, whereas AQFP circuits propagate data via transformers, which can occupy a large part of the gate area. Thus, DQFP circuits are more space-efficient than AQFP circuits. In this study, we optimized the circuit parameters for DQFP logic cells using numerical simulations from the viewpoint of excitation current margins, component parameter margins, and energy dissipation. We also designed the physical layout of the optimized DQFP cells, fabricated chips, and demonstrated basic DQFP circuits with the optimized cells.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic with zero static power and very small dynamic power due to adiabatic switching operations. In order to build large-scale digital circuits, we built AQFP logic cells using superconductor magnetic shields, which are necessary in order to avoid unwanted magnetic couplings between the cells and excitation currents. In preliminary experimental tests, we confirmed that the unwanted coupling became negligibly small thanks to the superconductor shields. As a demonstration, we designed a four-to-one multiplexor and a 16-junction full adder using the shielded logic cells. In both circuits, we confirmed correct logic operations with wide operation margins of excitation currents. These results indicate that large-scale AQFP digital circuits can be realized using the shielded logic cells.