Adiabatic quantum-flux-parametron (AQFP) is an ac-biased logic family noted for its extremely low switching energy of around 1.4 zJ per Josephson junction (JJ) at a clock frequency of 5 GHz. Therefore, the AQFP logic family provides a high-speed, ultra-low-energy alternative to CMOS technology. However, quantised flux, such as vortices, trapped in the superconductor film can adversely affect circuit operation. A conventional solution to vortices is the introduction of low potential holes, also known as moats, within the film. Although basic guidelines have been introduced from published circuits, there is currently no standard method for designing and analysing moats for AQFP circuits. The double gate process (DGP) is a double-active-layered niobium fabrication process that allows for more compact circuits. But the effects of quantised flux for AQFP circuits on both active layers are currently unknown. We use 3D parameter extraction software tools to analyse the effect of various moat structures for AQFP logic cells for DGP and improve layout and moat placement designs.
Adiabatic quantum-flux-parametron (AQFP) is an ac-biased logic family noted for its extremely low switching energy of around 1.4 zJ per Josephson junction (JJ) at a clock frequency of 5 GHz. Therefore, the AQFP logic family provides a high-speed, ultra-low-energy alternative to CMOS technology. However, quantised flux, such as vortices, trapped in the superconductor film can adversely affect circuit operation. A conventional solution to vortices is the introduction of low potential holes, also known as moats, within the film. Although basic guidelines have been introduced from published circuits, there is currently no standard method for designing and analysing moats for AQFP circuits. The double gate process (DGP) is a double-active-layered niobium fabrication process that allows for more compact circuits. But the effects of quantised flux for AQFP circuits on both active layers are currently unknown. We use 3D parameter extraction software tools to analyse the effect of various moat structures for AQFP logic cells for DGP and improve layout and moat placement designs.
Abstract Adiabatic quantum-flux-parametron (AQFP) is an ultra-low-power superconductor logic. In this study, we proposed and designed three-dimensional (3D) AQFP to achieve high circuit density and efficient interconnections. In 3D-AQFP, different AQFP logic circuits can be designed both over and under a ground plane (GP). The 3D-AQFP circuits are fabricated using the AIST 10 kA cm −2 Nb double gate process, in which two active layers are separated by a single GP. Followed by basic logic cell tests, we show an experimental demonstration of a 3D-XOR gate, the building block cells of which are vertically stacked to save circuit area and wiring length. The measurement results showed reasonable excitation current margins of more than ±16% for the 3D-XOR gate.
Adiabatic quantum-flux-parametron (AQFP) superconductor logic is a proven energy-efficient digital technology for various applications. To address the scalability challenges of this technology, we investigated AQFP shift registers with the AQFP footprint area reduced by 25% with respect to prior work and with the >2× denser overall circuit designs obtained by eliminating the previously used free space between the AQFPs. We also investigated AQFP cells with different designs of flux trapping moats in the superconducting ground plane as well as compact AQFP cells that took advantage of the smaller feature sizes available in the new fabrication process, SFQ5ee+, at MIT Lincoln Laboratory (MIT LL). This new process features nine planarized Nb layers with a 0.25 μm minimum linewidth. The fabricated circuits were tested in a liquid He immersion probe and a commercial closed-cycle cryocooler using a controlled cooling rate through the superconducting critical temperature,Tc. Using multiple thermal cycles, we investigated flux trapping in the dense AQFP shift registers as well as in the registers using the old (sparse) AQFP designs at two levels of the residual magnetic field, about 0.53 μT and about 1.2 μT. The sparse designs demonstrated 95% to almost 100% probability of operation after the cooldown and very wide operation margins, although the flux trapping probability was increasing with circuit complexities. The margins were similarly wide in the newer dense designs, but flux trapping probability that rendered the registers nonoperational was significantly, by an order of magnitude, higher in these denser circuits and was also very sensitive to the moats' shape and location. Our findings indicate that AQFP circuits are amendable to increasing the scale of integration and further densification, but a careful moat design and optimization are required to reduce flux trapping effects in the dense AQFP circuits.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is one of the most promising superconductor logic families as a candidate to achieve future energy-efficient high-performance information processing systems. The static power of AQFP logic is zero because of ac flux bias, and the switching energy is ∼zJ at 5 GHz due to adiabatic switching. In this study, we propose a design method using offset buffers to reduce the dimension of AQFP circuits; in particular, we focus on the reduction in the horizontal dimension (which is parallel to excitation current) because in AQFP circuits the horizontal dimension tends to be greater than the vertical dimension (which is perpendicular to excitation current). Offset buffers are buffers with offset input signals. The use of offset buffers enables us to eliminate constant cells (which generate constant 0 s and 1 s) from some logic gates, so that the horizontal dimension of logic gates such as AND and OR gates can be significantly reduced. We designed AND and OR gates with offset buffers, and demonstrated them with wide operating margins. Then, we designed and demonstrated a 4–16 decoder using the AND gate with an offset buffer. We found that the horizontal dimension and area of a 4–16 decoder can be reduced by 33% and 26%, respectively, via the use of offset buffers.
Abstract Adiabatic quantum-flux-parametron (AQFP) is an adiabatic logic based on the quantum-flux-parametron. It has extremely low switching energy, as well as high signal gain and high robustness. In this work, we present the development of an AQFP cell library using the MIT LL 100 μ A μ m −2 superconductor electronics fabrication process, SFQ5ee. Four types of basic sub-cells, i.e. buffer, inverter, constant, and branch, are designed as the building blocks for combinational AQFP logic cells. Taking advantage of the 8 metal layers, we place the dc superconducting quantum interference device (SQUID) part of a buffer above the ground plane and the signal transformer part below the ground plane to mitigate unwanted couplings. In addition, by vertically overlapping the signal transformer and the dc SQUID, the dimension of a buffer is reduced to 15 μ m × 20 μ m, which is only 30% of that of the conventional design. More complex AQFP logic cells, such as the majority gate, AND gate, and OR gate, are designed by arraying the sub-cells together. Correct operations and wide excitation current margins are confirmed for the established AQFP logic cells by both simulation and experiments.
We have been developing the adiabatic quantum-flux-parametron (AQFP), which is an ultra-low-power superconductor logic family. To date, somewhat large AQFP circuits, such as a 4-bit microprocessor and an 8-bit adder, have been demonstrated. To design much larger devices, space-efficient logic circuits are needed. Therefore, in a previous study, we proposed the directly coupled quantum-flux-parametron (DQFP). DQFP circuits propagate data via a direct connection, whereas AQFP circuits propagate data via transformers, which can occupy a large part of the gate area. Thus, DQFP circuits are more space-efficient than AQFP circuits. In this study, we optimized the circuit parameters for DQFP logic cells using numerical simulations from the viewpoint of excitation current margins, component parameter margins, and energy dissipation. We also designed the physical layout of the optimized DQFP cells, fabricated chips, and demonstrated basic DQFP circuits with the optimized cells.
Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The switching energy of an AQFP gate can be arbitrarily reduced via adiabatic switching. However, AQFP logic has somewhat long latency due to the multiphase clocking scheme, in which each logic operation requires a quarter clock cycle. The latency in AQFP logic should be improved in order to design complex digital circuits such as microprocessors. In the present paper, we propose a low-latency clocking scheme for AQFP logic, which we call delay-line clocking. In delay-line clocking, the latency for each logic operation is determined by the propagation delay of the excitation current, which can be much shorter than a quarter clock cycle. Our numerical simulation shows that AQFP gates can operate with a latency of only a few picoseconds. We fabricated an AQFP circuit adopting delay-line clocking using the 10 kA/cm2 Nb high-speed standard process provided by the National Institute of Advanced Industrial Science and Technology. The circuit was demonstrated at 4 GHz with a latency of 10 ps per gate. The above results indicate that delay-line clocking can significantly reduce the latency in AQFP logic.