Abstract Adiabatic quantum-flux-parametron (AQFP) logic is one of the most promising superconductor logic families as a candidate to achieve future energy-efficient high-performance information processing systems. The static power of AQFP logic is zero because of ac flux bias, and the switching energy is ∼zJ at 5 GHz due to adiabatic switching. In this study, we propose a design method using offset buffers to reduce the dimension of AQFP circuits; in particular, we focus on the reduction in the horizontal dimension (which is parallel to excitation current) because in AQFP circuits the horizontal dimension tends to be greater than the vertical dimension (which is perpendicular to excitation current). Offset buffers are buffers with offset input signals. The use of offset buffers enables us to eliminate constant cells (which generate constant 0 s and 1 s) from some logic gates, so that the horizontal dimension of logic gates such as AND and OR gates can be significantly reduced. We designed AND and OR gates with offset buffers, and demonstrated them with wide operating margins. Then, we designed and demonstrated a 4–16 decoder using the AND gate with an offset buffer. We found that the horizontal dimension and area of a 4–16 decoder can be reduced by 33% and 26%, respectively, via the use of offset buffers.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is one of the most promising superconductor logic families as a candidate to achieve future energy-efficient high-performance information processing systems. The static power of AQFP logic is zero because of ac flux bias, and the switching energy is ∼zJ at 5 GHz due to adiabatic switching. In this study, we propose a design method using offset buffers to reduce the dimension of AQFP circuits; in particular, we focus on the reduction in the horizontal dimension (which is parallel to excitation current) because in AQFP circuits the horizontal dimension tends to be greater than the vertical dimension (which is perpendicular to excitation current). Offset buffers are buffers with offset input signals. The use of offset buffers enables us to eliminate constant cells (which generate constant 0 s and 1 s) from some logic gates, so that the horizontal dimension of logic gates such as AND and OR gates can be significantly reduced. We designed AND and OR gates with offset buffers, and demonstrated them with wide operating margins. Then, we designed and demonstrated a 4–16 decoder using the AND gate with an offset buffer. We found that the horizontal dimension and area of a 4–16 decoder can be reduced by 33% and 26%, respectively, via the use of offset buffers.
Abstract Adiabatic quantum-flux-parametron (AQFP) is an adiabatic logic based on the quantum-flux-parametron. It has extremely low switching energy, as well as high signal gain and high robustness. In this work, we present the development of an AQFP cell library using the MIT LL 100 μ A μ m −2 superconductor electronics fabrication process, SFQ5ee. Four types of basic sub-cells, i.e. buffer, inverter, constant, and branch, are designed as the building blocks for combinational AQFP logic cells. Taking advantage of the 8 metal layers, we place the dc superconducting quantum interference device (SQUID) part of a buffer above the ground plane and the signal transformer part below the ground plane to mitigate unwanted couplings. In addition, by vertically overlapping the signal transformer and the dc SQUID, the dimension of a buffer is reduced to 15 μ m × 20 μ m, which is only 30% of that of the conventional design. More complex AQFP logic cells, such as the majority gate, AND gate, and OR gate, are designed by arraying the sub-cells together. Correct operations and wide excitation current margins are confirmed for the established AQFP logic cells by both simulation and experiments.
Abstract Adiabatic quantum flux parametron (AQFP) is energy-efficient superconducting logic that operates with zero static energy consumption and extremely small dynamic energy consumption thanks to the adiabatic switching of the logic gates. One drawback in AQFP logic circuits is the wire length and fan-out limitations because of the low driving ability of the logic gates, which results in a large circuit area and significant latency. In the present study, we propose AQFP boosters with high driving ability. Two types of AQFP boosters are proposed: one is composed of a parallel connection of AQFP buffers, and the other uses multistage buffers driven by one excitation clock. We evaluated the maximum wire length of the proposed boosters by circuit simulations, including thermal noises, and found that the maximum wire length is 3.9 mm for fan-out one and 1 mm for fan-out four. We implemented the boosters and demonstrated their correct operations at low-speed tests. We also demonstrated a 5-to-31 decoder using the proposed boosters. It was shown that the circuit area, latency, and energy consumption were improved by about 30% compared to the design without the boosters.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic with zero static power and very small dynamic power due to adiabatic switching operations. In order to build large-scale digital circuits, we built AQFP logic cells using superconductor magnetic shields, which are necessary in order to avoid unwanted magnetic couplings between the cells and excitation currents. In preliminary experimental tests, we confirmed that the unwanted coupling became negligibly small thanks to the superconductor shields. As a demonstration, we designed a four-to-one multiplexor and a 16-junction full adder using the shielded logic cells. In both circuits, we confirmed correct logic operations with wide operation margins of excitation currents. These results indicate that large-scale AQFP digital circuits can be realized using the shielded logic cells.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic stands as an energy-efficient superconductor logic family relying on ac excitations. Though a four-phase clocking scheme has been commonly applied to excite and clock AQFP circuits, the cost of multiple sources and long between-stage latency (a quarter clock cycle) remain unsatisfactory. These drawbacks are more severe for sequential logics, where feedback loops require both down-flow and reverse-flow AQFP gates, necessitating extra buffers and imposing a limit on operating depth at the same time. To overcome these restrictions, in this paper, we introduce a novel mixed clocking scheme for low-latency AQFP logic circuits allowing feedback loops. In particular, the down-flow part of the AQFP circuit is excited by an ac current through delay-lines, which can reduce the latency from input to output stages. Meanwhile, the reverse-flow part is clocked by 2 other ac currents with 90° phase difference to reduce the buffering gates. The proposed clocking scheme is first applied to a fundamental logic circuit, confirming correct functionality and low-latency operations for diverse feedback conditions. For experimental validation, we design and fabricate a 3-bit AQFP counter using the proposed clocking scheme based on an on-chip clock splitter. The circuit is examined at 4 GHz under 4.2 K temperature, where we obtain desired operations and wide excitation margins.
Adiabatic quantum flux parametron (AQFP) is a very energy-efficient superconductor logic. In AQFP logic, dynamic energy dissipation can be drastically reduced due to adiabatic switching operations using ac excitation currents. In the present study, we evaluated circuit yields using a large-scale AQFP circuit composed of as many as 10,000 AQFP gates with approximately 20,000 Josephson junctions. We measured eleven chips from four wafers and obtained circuit yields of 48% for 1,000-gate circuits and 22% for 10,000-gate circuits, respectively. In all the circuits, which worked correctly, the margins of excitation currents were as wide as approximately ±20%.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The latency of AQFP circuits is relatively long compared to that of other superconductor logic families and thus such circuits require low-latency clocking schemes. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current, and demonstrated a simple AQFP buffer chain that adopts delay-line clocking. However, it is unclear whether more complex AQFP circuits can adopt delay-line clocking. In the present study, we demonstrate AQFP logic gates (AND and XOR gates) that use delay-line clocking as a step towards implementing large-scale AQFP circuits with delay-line clocking. AND and XOR gates with a latency of approximately 20 ps per gate are shown to operate at up to 5 and 4 GHz, respectively, in experiments. We also demonstrate that delay-line clocking enables phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. The results indicate that delay-line clocking can enable low-latency, low-energy, large-scale AQFP circuits.