Abstract Adiabatic quantum-flux-parametron (AQFP) is an ultra-low-power superconductor logic. In this study, we proposed and designed three-dimensional (3D) AQFP to achieve high circuit density and efficient interconnections. In 3D-AQFP, different AQFP logic circuits can be designed both over and under a ground plane (GP). The 3D-AQFP circuits are fabricated using the AIST 10 kA cm −2 Nb double gate process, in which two active layers are separated by a single GP. Followed by basic logic cell tests, we show an experimental demonstration of a 3D-XOR gate, the building block cells of which are vertically stacked to save circuit area and wiring length. The measurement results showed reasonable excitation current margins of more than ±16% for the 3D-XOR gate.
Abstract Adiabatic quantum-flux-parametron (AQFP) is an ultra-low-power superconductor logic. In this study, we proposed and designed three-dimensional (3D) AQFP to achieve high circuit density and efficient interconnections. In 3D-AQFP, different AQFP logic circuits can be designed both over and under a ground plane (GP). The 3D-AQFP circuits are fabricated using the AIST 10 kA cm −2 Nb double gate process, in which two active layers are separated by a single GP. Followed by basic logic cell tests, we show an experimental demonstration of a 3D-XOR gate, the building block cells of which are vertically stacked to save circuit area and wiring length. The measurement results showed reasonable excitation current margins of more than ±16% for the 3D-XOR gate.
Abstract Adiabatic quantum-flux-parametron (AQFP) is an adiabatic logic based on the quantum-flux-parametron. It has extremely low switching energy, as well as high signal gain and high robustness. In this work, we present the development of an AQFP cell library using the MIT LL 100 μ A μ m −2 superconductor electronics fabrication process, SFQ5ee. Four types of basic sub-cells, i.e. buffer, inverter, constant, and branch, are designed as the building blocks for combinational AQFP logic cells. Taking advantage of the 8 metal layers, we place the dc superconducting quantum interference device (SQUID) part of a buffer above the ground plane and the signal transformer part below the ground plane to mitigate unwanted couplings. In addition, by vertically overlapping the signal transformer and the dc SQUID, the dimension of a buffer is reduced to 15 μ m × 20 μ m, which is only 30% of that of the conventional design. More complex AQFP logic cells, such as the majority gate, AND gate, and OR gate, are designed by arraying the sub-cells together. Correct operations and wide excitation current margins are confirmed for the established AQFP logic cells by both simulation and experiments.
Adiabatic quantum-flux-parametron (AQFP) is an ac-biased logic family noted for its extremely low switching energy of around 1.4 zJ per Josephson junction (JJ) at a clock frequency of 5 GHz. Therefore, the AQFP logic family provides a high-speed, ultra-low-energy alternative to CMOS technology. However, quantised flux, such as vortices, trapped in the superconductor film can adversely affect circuit operation. A conventional solution to vortices is the introduction of low potential holes, also known as moats, within the film. Although basic guidelines have been introduced from published circuits, there is currently no standard method for designing and analysing moats for AQFP circuits. The double gate process (DGP) is a double-active-layered niobium fabrication process that allows for more compact circuits. But the effects of quantised flux for AQFP circuits on both active layers are currently unknown. We use 3D parameter extraction software tools to analyse the effect of various moat structures for AQFP logic cells for DGP and improve layout and moat placement designs.
We have been developing the adiabatic quantum-flux-parametron (AQFP), which is an ultra-low-power superconductor logic family. To date, somewhat large AQFP circuits, such as a 4-bit microprocessor and an 8-bit adder, have been demonstrated. To design much larger devices, space-efficient logic circuits are needed. Therefore, in a previous study, we proposed the directly coupled quantum-flux-parametron (DQFP). DQFP circuits propagate data via a direct connection, whereas AQFP circuits propagate data via transformers, which can occupy a large part of the gate area. Thus, DQFP circuits are more space-efficient than AQFP circuits. In this study, we optimized the circuit parameters for DQFP logic cells using numerical simulations from the viewpoint of excitation current margins, component parameter margins, and energy dissipation. We also designed the physical layout of the optimized DQFP cells, fabricated chips, and demonstrated basic DQFP circuits with the optimized cells.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic with zero static power and very small dynamic power due to adiabatic switching operations. In order to build large-scale digital circuits, we built AQFP logic cells using superconductor magnetic shields, which are necessary in order to avoid unwanted magnetic couplings between the cells and excitation currents. In preliminary experimental tests, we confirmed that the unwanted coupling became negligibly small thanks to the superconductor shields. As a demonstration, we designed a four-to-one multiplexor and a 16-junction full adder using the shielded logic cells. In both circuits, we confirmed correct logic operations with wide operation margins of excitation currents. These results indicate that large-scale AQFP digital circuits can be realized using the shielded logic cells.
Abstract Superconductor logic families can operate with small power dissipation and are thus suitable as building blocks for various computing systems. In some applications, superconductor logic circuits should be designed using Josephson junctions with low I c values ( I c : critical current). For instance, lowering I c values enables qubit interface circuits to operate with very small power dissipation at ~10 mK and stochastic electronics to easily induce stochastic operations. In this study, we develop the AIST 1 kA cm −2 Nb planarized process (1KP) with a minimum critical current of 10 µA, dedicated to the design of qubit interface circuits and stochastic electronics. We also develop rapid single-flux-quantum (RSFQ) and adiabatic quantum-flux-parametron (AQFP) cell libraries using the 1KP. The power dissipation of RSFQ logic using the 1KP can be reduced to 3.2% of that for conventional RSFQ logic by reducing both I c values and a bias voltage. Furthermore, the amount of supply currents for AQFP circuits using the 1KP can be reduced to ~40% of that for conventional AQFP circuits due to a large mutual inductance between AQFP gates and excitation lines, which results from a reduction in I c and an increase in inductances. We demonstrate RSFQ and AQFP circuits fabricated by the 1KP at 4.2 K. These results indicate that RSFQ and AQFP circuits using the 1KP have the potential to be used for the design of qubit interface circuits and stochastic electronics.
Abstract We present a comprehensive overview of a design methodology and environment that we developed to enable the implementation of microprocessors and other complex logic circuits using the adiabatic quantum-flux-parametron (AQFP) superconductor logic family. The design environment is catered for both the AIST 10 kA cm −2 Nb high-speed standard process as well as the AIST 2.5 kA cm −2 Nb standard process (STP2). We detail each aspect of the design flow, highlighting improvements in cell design, and new developments in circuit retiming to reduce the number of synchronizing buffers in the circuit datapath. With retiming, we expect a 14–37% reduction in the overall Josephson junction (JJ) count for some benchmarks. Finally, we show the successful experimental demonstration of an arithmetic logic unit and data shifter for an AQFP microprocessor using the established methodology and environment. The demonstrated circuits show full functionality and wide excitation current margins of nearly ±30%, which corresponds well with simulation results.