Superconductor electronics fabrication technology developed at MIT Lincoln Laboratory enables the development of VLSI digital circuits with millions of Josephson junctions per square centimeter. However, conventional DC and multi-phase AC biasing techniques already encounter serious challenges for scaling circuits above several hundred thousand junctions. In this work, we propose a novel AC-based biasing scheme for RSFQ-type logic families requiring DC bias. The major step toward this scheme is a superconducting AC/DC rectifier which we introduced at ASC 2014. We proposed to connect the rectifiers to “payload cells” via superconducting inductors with large inductance in order to reduce parasitic effects of flux quantization. Recently, we discovered that this powering scheme works even better at a much lower value of the inductance, when it is just sufficient to hold only one or two flux quanta in the inductive loop between the converter and the payload. In this case, flux quantization in the loop becomes beneficial because the value of current fed into the payload is defined by the value of the coupling inductance. Therefore, our AC/SFQ converter powers the payload cell by single flux quanta rather than by DC current. Such mode of operation is extremely energy efficient because energy is used only to recover the flux quantum consumed by the cell during the logic operation. We present designs of AC/SFQ converters comprising an AC/DC rectifier and a current conditioning circuit which we termed an SFQ filter. We also present test results and demonstrate AC/SFQ powering a payload circuit using circuits fabricated in a new, 150-nm node of Lincoln Laboratory fabrication technology using self-shunted Nb/AlOx-Al/Nb Josephson junctions with 600 μA/μm2critical current density and 200 nm minimum linewidth of inductors.
Superconductor electronics fabrication technology developed at MIT Lincoln Laboratory enables the development of VLSI digital circuits with millions of Josephson junctions per square centimeter. However, conventional DC and multi-phase AC biasing techniques already encounter serious challenges for scaling circuits above several hundred thousand junctions. In this work, we propose a novel AC-based biasing scheme for RSFQ-type logic families requiring DC bias. The major step toward this scheme is a superconducting AC/DC rectifier which we introduced at ASC 2014. We proposed to connect the rectifiers to “payload cells” via superconducting inductors with large inductance in order to reduce parasitic effects of flux quantization. Recently, we discovered that this powering scheme works even better at a much lower value of the inductance, when it is just sufficient to hold only one or two flux quanta in the inductive loop between the converter and the payload. In this case, flux quantization in the loop becomes beneficial because the value of current fed into the payload is defined by the value of the coupling inductance. Therefore, our AC/SFQ converter powers the payload cell by single flux quanta rather than by DC current. Such mode of operation is extremely energy efficient because energy is used only to recover the flux quantum consumed by the cell during the logic operation. We present designs of AC/SFQ converters comprising an AC/DC rectifier and a current conditioning circuit which we termed an SFQ filter. We also present test results and demonstrate AC/SFQ powering a payload circuit using circuits fabricated in a new, 150-nm node of Lincoln Laboratory fabrication technology using self-shunted Nb/AlOx-Al/Nb Josephson junctions with 600 μA/μm2critical current density and 200 nm minimum linewidth of inductors.
Recent progress on reciprocal quantum logic (RQL) has renewed interest in ac powering of superconductor digital circuits, which had been abandoned since the famous IBM project of 1970s. In this paper, we propose and demonstrate new ac-biased single flux quantum (SFQ) circuits, and search for synergy of ac and currently dominating dc biasing schemes. As the first step, we suggest an on-chip ac/dc converter capable of feeding a few dc-biased gates surrounded by their ac-biased counterparts. As the second step, we introduce and present the first successful demonstration of a new ac-powered circuit-an 8192-bit shift register with over 32800 Josephson junctions (JJs) and JJ density of about 6 · 105 JJ per cm2. We suggest a few niche applications for this type of ac-biased circuits, which require high clock rates. For example, these circuits, scalable to millions of JJs per chip, can serve as a convenient benchmark for new SFQ fabrication technology nodes, allowing the operating margins of individual cells to be extracted and thus “visualize” individual fabrication defects and flux trapping events. The circuit can also be developed into a megapixel imaging array for a magnetic field microscope.
Flux transformers are the necessary component of all superconductor digital integrated circuits utilizing flux biasing and ac power excitation and clocking of logic cells, e.g., adiabatic quantum flux parametron (AQFP), reciprocal quantum logic (RQL), superconducting sensor arrays, qubits, etc. On average, one transformer is required per one Josephson junction. We consider limitations to the integration scale (device number density) imposed by the critical current of the ac power transmission lines (primary of the transformers) and cross-coupling between the adjacent transformers. The former sets the minimum linewidth and the mutual coupling length in the transformer, whereas the latter sets the minimum spacing between the transformers. Decreasing linewidth of superconducting (Nb) wires increases kinetic inductance of the transformer's secondary, decreasing its length and mutual coupling to the primary. This limits the minimum size. As a result, there is a minimum linewidth${{\boldsymbol{w}}}_{\mathbf{min}}\sim $100 nm, which determines the maximum achievable scale of integration. Using AQFP circuits as an example, we calculate dependences of the AQFP number density on linewidth for various types of microstrip-based and stripline-based transformers and inductors available in the SFQ5ee fabrication process developed at MIT Lincoln Laboratory, and estimate the maximum circuit density as a few million AQFPs per cm2. We propose an advanced fabrication process for a 10× increase in the density of AQFP and other ac-powered circuits. In this process, inductors are formed from a patterned bilayer of a geometrical inductance material, Nb, deposited over a layer of high kinetic inductance material, e.g., NbN. Individual pattering of the bilayer layers allows to create stripline inductors in a wide range of inductances, from the low values typical to Nb striplines to the high values typical for NbN thin films, and preserve sufficient mutual coupling in stripline transformers with extremely low cross-talk. Energy efficiency of ac-powered circuits is limited by dielectric losses in the ac power transmissions lines. Problems of scaling associated with multiphase ac power distribution are discussed.
Biasing remains one of the key scalability bottle necks in superconducting digital circuits, as traditional DC bias networks impose excessive power dissipation, large direct current requirements resulting in significant power overhead. Fast Phase Logic (FPL), an all-Josephson Junction (JJ) logic family, achieves ultra-high density by eliminating resistors and large inductors; however, existing FPL designs still rely on DC bias. This paper introduces a novel architecture: AC-biased FPL (ACFPL), which integrates single-phase AC/SFQ converters with FPL cells to deliver bias currents as quantized pulses, thereby eliminating the need for a global DC distribution network. Circuit-level simulations at 10 GHz demonstrate that AC biasing achieves up to 25× lower power consumption compared to DC bias for RSFQ circuits, and 14.3× reduction in power consumption for FPL circuits in our design-under-test (DUT), which combines FPL JTL, FPL DFF, and FPL AND cells. These results estab lish ACFPL as a scalable and energy-efficient alternative for large-scale superconducting digital systems, effectively combining compact FPL cell design with practical AC/SFQ bias delivery, allowing superconductor VLSI.
High current requirements in single flux quantum (SFQ) circuits pose scalability challenges, contributing to issues such as high thermal loads, static power dissipation, and increased sensitivity to flux trapping under non-ideal shielding or cool down conditions. AC biasing, successfully used in other superconductive logic families, has been integrated into rapid single flux quantum (RSFQ) circuits and typically includes AC-to-DC converters, introducing area and complexity overhead. This work proposes an alternative method for applying AC biasing to existing RSFQ circuits using inductively coupled bias junctions, eliminating the need for AC-to-DC converters. This approach also combines resistive DC biasing with inductive AC biasing, reducing static power dissipation. The proposed approach targets clock splitters, which are significant contributors to on-chip current demand, achieving an average 94% reduction in splitter current and a 62% reduction in overall system current with a Josephson junction overhead of 6.5%. The technique is compatible with conventional RSFQ system architectures and logic families while significantly enhancing energy efficiency and scalability.
Josephson junction-based superconducting logic families have been proposed to implement analog and digital signals, which can achieve low energy dissipation and ultra-fast switching speed. There are two representative technologies: DC-biased RSFQ (rapid single flux quantum) technology and its variants that achieve a verified speed of 370 Ghz, and AC-biased AQFP (adiabatic quantum-flux-parametron) that achieves an energy dissipation near quantum limits. Despite extraordinary characteristics of the superconducting logic families, many technical challenges remain, including the choice of circuit fabrics and architectures that utilize the SFQ technology and the development of effective design automation methodologies and tools. This paper presents our work on developing design flows and tools for DC- and AC-biased SFQ circuits, leveraging unique characteristics and design requirements of the SFQ logic families. More precisely, physical design algorithms, including placement, clock tree routing, and signal routing algorithms targeting RSFQ circuits are presented first. Next, a majority/minority gate-based automatic synthesis framework targeting AQFP logic circuits is described. Finally, experimental results to demonstrate the efficacy of the proposed framework and tools are presented.
We develop an ac-biased shift register introduced in our previous work (V. K. Semenov et al., IEEE Trans. Appl. Supercond., vol. 25, no. 3, 1301507, June 2015) into a benchmark circuit for evaluation of superconductor electronics fabrication technology. The developed testing technique allows for extracting margins of all individual cells in the shift register, which in turn makes it possible to estimate statistical distribution of Josephson junctions (JJs) in the circuit. We applied this approach to successfully test registers having 8-, 16-, 36-, and 202 thousand cells and, respectively, about 33-, 65-, 144-, and 809 thousand JJs. The circuits were fabricated at MIT Lincoln Laboratory, using a fully planarized process, 0.4-μm inductor linewidth and 1.33 × 106cm-2junction density. They are presently the largest operational superconducting SFQ circuits ever made. The developed technique distinguishes between “hard” defects (fabrication-related) and “soft” defects (measurement-related) and locates them in the circuit. The “soft” defects are specific to superconducting circuits and caused by magnetic flux trapping either inside the active cells or in the dedicated flux-trapping moats near the cells. The number and distribution of “soft” defects depend on the ambient magnetic field and vary with thermal cycling even if done in the same magnetic environment.