Biasing remains one of the key scalability bottle necks in superconducting digital circuits, as traditional DC bias networks impose excessive power dissipation, large direct current requirements resulting in significant power overhead. Fast Phase Logic (FPL), an all-Josephson Junction (JJ) logic family, achieves ultra-high density by eliminating resistors and large inductors; however, existing FPL designs still rely on DC bias. This paper introduces a novel architecture: AC-biased FPL (ACFPL), which integrates single-phase AC/SFQ converters with FPL cells to deliver bias currents as quantized pulses, thereby eliminating the need for a global DC distribution network. Circuit-level simulations at 10 GHz demonstrate that AC biasing achieves up to 25× lower power consumption compared to DC bias for RSFQ circuits, and 14.3× reduction in power consumption for FPL circuits in our design-under-test (DUT), which combines FPL JTL, FPL DFF, and FPL AND cells. These results estab lish ACFPL as a scalable and energy-efficient alternative for large-scale superconducting digital systems, effectively combining compact FPL cell design with practical AC/SFQ bias delivery, allowing superconductor VLSI.
Biasing remains one of the key scalability bottle necks in superconducting digital circuits, as traditional DC bias networks impose excessive power dissipation, large direct current requirements resulting in significant power overhead. Fast Phase Logic (FPL), an all-Josephson Junction (JJ) logic family, achieves ultra-high density by eliminating resistors and large inductors; however, existing FPL designs still rely on DC bias. This paper introduces a novel architecture: AC-biased FPL (ACFPL), which integrates single-phase AC/SFQ converters with FPL cells to deliver bias currents as quantized pulses, thereby eliminating the need for a global DC distribution network. Circuit-level simulations at 10 GHz demonstrate that AC biasing achieves up to 25× lower power consumption compared to DC bias for RSFQ circuits, and 14.3× reduction in power consumption for FPL circuits in our design-under-test (DUT), which combines FPL JTL, FPL DFF, and FPL AND cells. These results estab lish ACFPL as a scalable and energy-efficient alternative for large-scale superconducting digital systems, effectively combining compact FPL cell design with practical AC/SFQ bias delivery, allowing superconductor VLSI.
Superconductor electronics fabrication technology developed at MIT Lincoln Laboratory enables the development of VLSI digital circuits with millions of Josephson junctions per square centimeter. However, conventional DC and multi-phase AC biasing techniques already encounter serious challenges for scaling circuits above several hundred thousand junctions. In this work, we propose a novel AC-based biasing scheme for RSFQ-type logic families requiring DC bias. The major step toward this scheme is a superconducting AC/DC rectifier which we introduced at ASC 2014. We proposed to connect the rectifiers to “payload cells” via superconducting inductors with large inductance in order to reduce parasitic effects of flux quantization. Recently, we discovered that this powering scheme works even better at a much lower value of the inductance, when it is just sufficient to hold only one or two flux quanta in the inductive loop between the converter and the payload. In this case, flux quantization in the loop becomes beneficial because the value of current fed into the payload is defined by the value of the coupling inductance. Therefore, our AC/SFQ converter powers the payload cell by single flux quanta rather than by DC current. Such mode of operation is extremely energy efficient because energy is used only to recover the flux quantum consumed by the cell during the logic operation. We present designs of AC/SFQ converters comprising an AC/DC rectifier and a current conditioning circuit which we termed an SFQ filter. We also present test results and demonstrate AC/SFQ powering a payload circuit using circuits fabricated in a new, 150-nm node of Lincoln Laboratory fabrication technology using self-shunted Nb/AlOx-Al/Nb Josephson junctions with 600 μA/μm2critical current density and 200 nm minimum linewidth of inductors.
Abstract Fast phase logic (FPL) is a novel digital superconductor electronic (SCE) logic family that employs multiple junction types, including switching 0-Josephson junctions (0-JJs), non-switching 0-JJ stacks, and π-JJs. FPL enables flexible, automatable cell layouts, faster pulse propagation, reduced bias current via phaseshifting π-JJs, and minimized inductive loops, thereby reducing susceptibility to trapped flux and crosstalk.A fabrication process to support FPL is proposed. NbTiN superconductors offer small grain sizes, smooth surfaces, and thermal stability up to 400 ○ C, while high-Jc, self-shunted JJs enable compact devices. AlN dielectrics provide good crystal matching to NbTiN, improving superconducting properties. Projections indicate that FPL, combined with the proposed process, can achieve a two-order-of-magnitude increase in integration density over conventional RSFQ logic and a five-fold reduction in supply current. The increased density reduces latency and improves computational throughput, while NbTiN-based devices provide higher output voltage and impedance, improving compatibility with CMOS circuits. Further fabrication advancements, such as higher-Jc NbTiN-based JJs, higher processing temperatures, and stacked JJ structures, could enhance FPL implementation and scalability toward very large-scale integration (VLSI). FPL has the potential to significantly advance SCE technology, with near-term applications in accelerator cores for signal processing and artificial intelligence, and long-term potential in supercomputing. Its advantages are evaluated through an architectural study of a fast Fourier transform (FFT) circuit, with comparisons to CMOS and SFQ technologies for digital electronics.
High current requirements in single flux quantum (SFQ) circuits pose scalability challenges, contributing to issues such as high thermal loads, static power dissipation, and increased sensitivity to flux trapping under non-ideal shielding or cool down conditions. AC biasing, successfully used in other superconductive logic families, has been integrated into rapid single flux quantum (RSFQ) circuits and typically includes AC-to-DC converters, introducing area and complexity overhead. This work proposes an alternative method for applying AC biasing to existing RSFQ circuits using inductively coupled bias junctions, eliminating the need for AC-to-DC converters. This approach also combines resistive DC biasing with inductive AC biasing, reducing static power dissipation. The proposed approach targets clock splitters, which are significant contributors to on-chip current demand, achieving an average 94% reduction in splitter current and a 62% reduction in overall system current with a Josephson junction overhead of 6.5%. The technique is compatible with conventional RSFQ system architectures and logic families while significantly enhancing energy efficiency and scalability.
Abstract Energy-efficient rapid single flux quantum (ERSFQ) circuits suppress the dominant static power dissipation of Rapid SFQ logic by replacing bias resistors with current-limiting bias Josephson junctions (JJs) and inductors. In practice, however, these JJs introduce power dissipation in the DC bias network due to switching events required to correct data-dependent phase imbalances, with dissipation often comparable to that of dynamic power. This paper presents xeSFQ, a new SFQ logic family that integrates alternating SFQ (xSFQ) encoding with ERSFQ biasing. By enforcing a single pulse per line per logical cycle, xeSFQ maintains uniform phase across the circuit, thereby eliminating bias JJ switching during operation and achieving zero bias network power dissipation. Extensive analog simulations and logic synthesis results, from individual gates to ISCAS and EPFL benchmarks, validate this hypothesis and demonstrate the efficiency and scalability advantages of the proposed approach.
Abstract Superconductor Electronics (SCE) is a fast and power-efficient technology with great potential for overcoming conventional CMOS electronics’ scaling limits. Nevertheless, the primary challenge confronting SCE today is its integration level, which lags several orders of magnitude behind CMOS circuits. In this study, we have innovated and simulated a novel logic family grounded in the principles of phase shifts occurring in 0 and π Josephson junctions. The fast phase logic (FPL) eliminates the need for large inductor loops and shunt resistances by combining the half-flux and phase logic. Therefore, the Josephson junction (JJ) area only limits the integration density. The cells designed with this paradigm are fast, and the clock-to-Q delay for logic cells is about 4ps. While maintaining over 50% parameter margins for wiring cells. This logic is power efficient and can increase the integration by at least 100×in the SCE chips.
Recent progress on reciprocal quantum logic (RQL) has renewed interest in ac powering of superconductor digital circuits, which had been abandoned since the famous IBM project of 1970s. In this paper, we propose and demonstrate new ac-biased single flux quantum (SFQ) circuits, and search for synergy of ac and currently dominating dc biasing schemes. As the first step, we suggest an on-chip ac/dc converter capable of feeding a few dc-biased gates surrounded by their ac-biased counterparts. As the second step, we introduce and present the first successful demonstration of a new ac-powered circuit-an 8192-bit shift register with over 32800 Josephson junctions (JJs) and JJ density of about 6 · 105 JJ per cm2. We suggest a few niche applications for this type of ac-biased circuits, which require high clock rates. For example, these circuits, scalable to millions of JJs per chip, can serve as a convenient benchmark for new SFQ fabrication technology nodes, allowing the operating margins of individual cells to be extracted and thus “visualize” individual fabrication defects and flux trapping events. The circuit can also be developed into a megapixel imaging array for a magnetic field microscope.