Abstract Superconductor Electronics (SCE) is a fast and power-efficient technology with great potential for overcoming conventional CMOS electronics’ scaling limits. Nevertheless, the primary challenge confronting SCE today is its integration level, which lags several orders of magnitude behind CMOS circuits. In this study, we have innovated and simulated a novel logic family grounded in the principles of phase shifts occurring in 0 and π Josephson junctions. The fast phase logic (FPL) eliminates the need for large inductor loops and shunt resistances by combining the half-flux and phase logic. Therefore, the Josephson junction (JJ) area only limits the integration density. The cells designed with this paradigm are fast, and the clock-to-Q delay for logic cells is about 4ps. While maintaining over 50% parameter margins for wiring cells. This logic is power efficient and can increase the integration by at least 100×in the SCE chips.
Abstract Superconductor Electronics (SCE) is a fast and power-efficient technology with great potential for overcoming conventional CMOS electronics’ scaling limits. Nevertheless, the primary challenge confronting SCE today is its integration level, which lags several orders of magnitude behind CMOS circuits. In this study, we have innovated and simulated a novel logic family grounded in the principles of phase shifts occurring in 0 and π Josephson junctions. The fast phase logic (FPL) eliminates the need for large inductor loops and shunt resistances by combining the half-flux and phase logic. Therefore, the Josephson junction (JJ) area only limits the integration density. The cells designed with this paradigm are fast, and the clock-to-Q delay for logic cells is about 4ps. While maintaining over 50% parameter margins for wiring cells. This logic is power efficient and can increase the integration by at least 100×in the SCE chips.
Abstract Fast phase logic (FPL) is a novel digital superconductor electronic (SCE) logic family that employs multiple junction types, including switching 0-Josephson junctions (0-JJs), non-switching 0-JJ stacks, and π-JJs. FPL enables flexible, automatable cell layouts, faster pulse propagation, reduced bias current via phaseshifting π-JJs, and minimized inductive loops, thereby reducing susceptibility to trapped flux and crosstalk.A fabrication process to support FPL is proposed. NbTiN superconductors offer small grain sizes, smooth surfaces, and thermal stability up to 400 ○ C, while high-Jc, self-shunted JJs enable compact devices. AlN dielectrics provide good crystal matching to NbTiN, improving superconducting properties. Projections indicate that FPL, combined with the proposed process, can achieve a two-order-of-magnitude increase in integration density over conventional RSFQ logic and a five-fold reduction in supply current. The increased density reduces latency and improves computational throughput, while NbTiN-based devices provide higher output voltage and impedance, improving compatibility with CMOS circuits. Further fabrication advancements, such as higher-Jc NbTiN-based JJs, higher processing temperatures, and stacked JJ structures, could enhance FPL implementation and scalability toward very large-scale integration (VLSI). FPL has the potential to significantly advance SCE technology, with near-term applications in accelerator cores for signal processing and artificial intelligence, and long-term potential in supercomputing. Its advantages are evaluated through an architectural study of a fast Fourier transform (FFT) circuit, with comparisons to CMOS and SFQ technologies for digital electronics.
Single flux quantum (SFQ) technology has garnered significant attention due to its low switching power and high operational speed. Researchers have been actively pursuing more advanced devices and technologies to further reduce the reliance on inductors, bias, and dynamic power. Recently, innovative magnetic Josephson junction devices have emerged, enhancing the field of superconductor electronics logic. This article introduces a novel cell library design that relies entirely on Josephson junctions, showing promising potential for eliminating the need for inductors in conventional SFQ cells. This results in a 55% reduction in cell size and an 80% decrease in both static and dynamic power consumption. The proposed library implements a half flux quantum logic, where each pulse duration is half that of a SFQ pulse. This article presents the schematics of the basic cells, emphasizing critical circuit parameters and their margins. In addition, it examines layout blueprints, showcasing the advantageous area-saving characteristics of the proposed design.
Biasing remains one of the key scalability bottle necks in superconducting digital circuits, as traditional DC bias networks impose excessive power dissipation, large direct current requirements resulting in significant power overhead. Fast Phase Logic (FPL), an all-Josephson Junction (JJ) logic family, achieves ultra-high density by eliminating resistors and large inductors; however, existing FPL designs still rely on DC bias. This paper introduces a novel architecture: AC-biased FPL (ACFPL), which integrates single-phase AC/SFQ converters with FPL cells to deliver bias currents as quantized pulses, thereby eliminating the need for a global DC distribution network. Circuit-level simulations at 10 GHz demonstrate that AC biasing achieves up to 25× lower power consumption compared to DC bias for RSFQ circuits, and 14.3× reduction in power consumption for FPL circuits in our design-under-test (DUT), which combines FPL JTL, FPL DFF, and FPL AND cells. These results estab lish ACFPL as a scalable and energy-efficient alternative for large-scale superconducting digital systems, effectively combining compact FPL cell design with practical AC/SFQ bias delivery, allowing superconductor VLSI.
Superconductive logic based on Josephson junctions (JJ) is a promising technology for energy efficient supercomputers and cloud computing. This technology can deliver significant improvements in performance and energy efficiency as compared to CMOS. Superconductive circuits, however, suffer from low density integration as compared to CMOS, primarily due to the limited scalability of the inductors. To improve the scalability of superconductive logic, a logic family based on a novel JJ technology,$2\phi $-JJ, has been proposed that eliminates the inductors. In this brief, three circuits are presented which exploit this scalable inductor-less technology. This novel$2\phi $-JJ technology represents the data as half flux quantum (HFQ) pulses, which improves the energy efficiency and speed as compared to standard superconductive logic such as rapid single flux quantum (RSFQ). Unlike RSFQ, the proposed circuits dynamically switch upon receiving an HFQ pulse, saving energy. These$2\phi $-JJ logic circuits operate 2.25X faster and require 2.6X less energy as compared to RSFQ.
Magnetic flux quantization in superconductors allows the implementation of fast and energy-efficient digital superconducting circuits. However, the information representation in magnetic flux severely limits their functional density presenting a long-standing problem. Here we introduce a concept of superconducting digital circuits that do not utilize magnetic flux and have no inductors. We argue that neither the use of geometric nor kinetic inductance is promising for the deep scaling of superconducting circuits. The key idea of our approach is the utilization of bistable Josephson structures allowing the presentation of information in Josephson energy. Since the proposed circuits functionally rely on Josephson junctions only, they can be called all-Josephson junction (all-JJ) circuits. We consider the design methodology of the all-JJ circuits utilizing recently developed 2ϕ Josephson junctions for simplicity, though the bistability can be obtained with the other types of magnetic junctions like ϕ- or 0−π, or by using combinations of conventional 0- and π-junctions. Besides some broadly used basic cells, we present an all-JJ 8-bit parallel adder confirming the applicability of the proposed approach to the design of complex logic circuits.
Abstract We review the existing fabrication processes for superconductor digital electronics and describe approaches to increasing the scale of integration of superconducting digital circuits from the current level of about one million Josephson junctions (JJs) on a 1-cm 2 chip toward ten million JJs per chip. We present designs of ac-clocked Single Flux Quantum (SFQ) shift registers, convenient benchmarking circuits, in a 250-nm-linewidth superconductor electronics fabrication process developed recently at MIT Lincoln Laboratory (MIT LL). For shift registers using resistively shunted JJs with Josephson critical current density, J c of 100 μA/μm 2 , we achieved a record-high circuit density of 4.2·10 6 JJs per cm 2 , a factor of three higher than the previous record obtained in the MIT LL 350-nm-linewidth SFQ5ee process. Using self-shunted JJs with J c of 600 μA/μm 2 , we increased this record circuit density to 7.4·10 6 JJs per cm 2 .