Single flux quantum (SFQ) technology has garnered significant attention due to its low switching power and high operational speed. Researchers have been actively pursuing more advanced devices and technologies to further reduce the reliance on inductors, bias, and dynamic power. Recently, innovative magnetic Josephson junction devices have emerged, enhancing the field of superconductor electronics logic. This article introduces a novel cell library design that relies entirely on Josephson junctions, showing promising potential for eliminating the need for inductors in conventional SFQ cells. This results in a 55% reduction in cell size and an 80% decrease in both static and dynamic power consumption. The proposed library implements a half flux quantum logic, where each pulse duration is half that of a SFQ pulse. This article presents the schematics of the basic cells, emphasizing critical circuit parameters and their margins. In addition, it examines layout blueprints, showcasing the advantageous area-saving characteristics of the proposed design.
Single flux quantum (SFQ) technology has garnered significant attention due to its low switching power and high operational speed. Researchers have been actively pursuing more advanced devices and technologies to further reduce the reliance on inductors, bias, and dynamic power. Recently, innovative magnetic Josephson junction devices have emerged, enhancing the field of superconductor electronics logic. This article introduces a novel cell library design that relies entirely on Josephson junctions, showing promising potential for eliminating the need for inductors in conventional SFQ cells. This results in a 55% reduction in cell size and an 80% decrease in both static and dynamic power consumption. The proposed library implements a half flux quantum logic, where each pulse duration is half that of a SFQ pulse. This article presents the schematics of the basic cells, emphasizing critical circuit parameters and their margins. In addition, it examines layout blueprints, showcasing the advantageous area-saving characteristics of the proposed design.
Superconductive logic based on Josephson junctions (JJ) is a promising technology for energy efficient supercomputers and cloud computing. This technology can deliver significant improvements in performance and energy efficiency as compared to CMOS. Superconductive circuits, however, suffer from low density integration as compared to CMOS, primarily due to the limited scalability of the inductors. To improve the scalability of superconductive logic, a logic family based on a novel JJ technology,$2\phi $-JJ, has been proposed that eliminates the inductors. In this brief, three circuits are presented which exploit this scalable inductor-less technology. This novel$2\phi $-JJ technology represents the data as half flux quantum (HFQ) pulses, which improves the energy efficiency and speed as compared to standard superconductive logic such as rapid single flux quantum (RSFQ). Unlike RSFQ, the proposed circuits dynamically switch upon receiving an HFQ pulse, saving energy. These$2\phi $-JJ logic circuits operate 2.25X faster and require 2.6X less energy as compared to RSFQ.
The all-JJ logic family is a promising area and power efficient, scalable single flux quantum (SFQ) technology for application to exascale supercomputers. All-JJ superconductive logic is based on a superconductor-ferromagnet-superconductor (SFS) bistable JJ, enabling nanometer feature sizes in VLSI complexity superconductive systems. In this paper, a mechanical analogy is proposed to describe the dynamic behavior of these bistable JJs. Novel all-JJ logic gates, such as TFF, DFF, OR, AND, and NOT gates, are presented here. All-JJ circuits are composed of bistable JJs, standard JJs, and bias currents, not requiring large inductors within the storage loops. All-JJ logic cells exhibit less delay and power than standard SFQ cells with the same critical current density. All-JJ systems can operate at high frequencies due to the small capacitance of the SFS JJ. A complex all-JJ circuit from the suite of ISCAS'85 benchmark circuits is also characterized. This complex all-JJ circuit exhibits less delay and power as compared to standard SFQ logic. The bias current in a conventional benchmark circuit and all-JJ benchmark circuit is, respectively, 22 mA and 13 mA. The delay of each cell within the conventional benchmark circuit and all-JJ benchmark circuit is, respectively, approximately 20 and 8 ps. A parasitic inductance in series with the JJs disturbs the current distribution within the all-JJ circuits while degrading the margins. To suppress the effects of this parasitic inductance on SFS JJs, small linear inductors are added to manage the current distribution and improve the parameter margins.
Abstract Superconductor Electronics (SCE) is a fast and power-efficient technology with great potential for overcoming conventional CMOS electronics’ scaling limits. Nevertheless, the primary challenge confronting SCE today is its integration level, which lags several orders of magnitude behind CMOS circuits. In this study, we have innovated and simulated a novel logic family grounded in the principles of phase shifts occurring in 0 and π Josephson junctions. The fast phase logic (FPL) eliminates the need for large inductor loops and shunt resistances by combining the half-flux and phase logic. Therefore, the Josephson junction (JJ) area only limits the integration density. The cells designed with this paradigm are fast, and the clock-to-Q delay for logic cells is about 4ps. While maintaining over 50% parameter margins for wiring cells. This logic is power efficient and can increase the integration by at least 100×in the SCE chips.
Superconductor electronics fabrication technology developed at MIT Lincoln Laboratory enables the development of VLSI digital circuits with millions of Josephson junctions per square centimeter. However, conventional DC and multi-phase AC biasing techniques already encounter serious challenges for scaling circuits above several hundred thousand junctions. In this work, we propose a novel AC-based biasing scheme for RSFQ-type logic families requiring DC bias. The major step toward this scheme is a superconducting AC/DC rectifier which we introduced at ASC 2014. We proposed to connect the rectifiers to “payload cells” via superconducting inductors with large inductance in order to reduce parasitic effects of flux quantization. Recently, we discovered that this powering scheme works even better at a much lower value of the inductance, when it is just sufficient to hold only one or two flux quanta in the inductive loop between the converter and the payload. In this case, flux quantization in the loop becomes beneficial because the value of current fed into the payload is defined by the value of the coupling inductance. Therefore, our AC/SFQ converter powers the payload cell by single flux quanta rather than by DC current. Such mode of operation is extremely energy efficient because energy is used only to recover the flux quantum consumed by the cell during the logic operation. We present designs of AC/SFQ converters comprising an AC/DC rectifier and a current conditioning circuit which we termed an SFQ filter. We also present test results and demonstrate AC/SFQ powering a payload circuit using circuits fabricated in a new, 150-nm node of Lincoln Laboratory fabrication technology using self-shunted Nb/AlOx-Al/Nb Josephson junctions with 600 μA/μm2critical current density and 200 nm minimum linewidth of inductors.
A single flux quantum (SFQ) logic cell library has been developed for the 10kA/cm2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5kA/cm2 to 10kA/cm2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100GHz.
Superconductor single flux quantum (SFQ) technology is one of the promising candidates for energy-efficient high-performance computing. A new generation of SFQ logics, Reciprocal Quantum Logic (RQL) with no static power dissipation in bias resistors, offers an opportunity to dramatically decrease energy consumption in superconductor processors. Although several low complexity RQL processing units have already been demonstrated, the use of RQL for local storage design has not been explored yet. The objective of this dissertation is to design on-chip local storage structures such as memory, register files, and caches with RQL technology and analyze their energy efficiency, complexity, and performance characteristics. The physical chip design of these RQL storage units is not feasible at this point because both CAD tools for physical VLSI chip design and as well as a target fabrication process are under development at Northrop-Grumman Systems Corp. (Baltimore, MD) and MIT Lincoln Laboratory, respectively. In order to achieve our goal, the layout-aware cell-level design process using VHDL RQL cell library developed at the Ultra High Speed Computing Lab in Stony Brook University has been used. The SBU VHDL RQL cell library specifies the dynamic and stand-by energy consumption, latency, JJ complexity, and approximate sizes of individual cells based on the input received from the JJ-level RQL designers. Clock propagation skew and wire delays are accounted for during circuit simulation. The circuit simulation is done with Mentor Graphics design and verification tools. As a result of the work, key characteristics of the 8.5 GHz multiported RQL storage structures with their capacity in the range of 1-4 kbit have been determined. The average energy consumption of the RQL storage designs is ~3.0-9.5 fJ/bit/operation at room temperature and the cryo-cooling efficiency is 0.1%. The data from this dissertation also reveal the critical issues that need to be considered in the RQL storage design. These will be helpful for further development on superconductor VLSI design. | 124 pages