We report on technique and results for superconductor electronics fabrication process, featuring customizable number of planarized superconducting layers. The novel technique enhanced yield on stackable vias of our standard planarized process (RIPPLE) by eliminating the need for an additional deposition of aluminum as an etch stop in the metal-via stack. The drawback of the previous approach was the difficulty in processing aluminum using either wet or dry etch mechanisms. Here, we discuss details of the novel fabrication process flow and its realization for 4.5 kA/cm2 fabrication process with six Nb layers with two fully planarized layers. We report test results of various planarization diagnostics structures, accounting the influence of topology on Josephson junction quality, as well as yield and critical current of via stacks. We also report on inductance measurement results providing information on interlayer dielectric thickness for planarized layers; confirming a good uniformity over the wafer. Basic components of superconducting logic such as dc/SFQ, SFQ/dc converters, Josephson transmission lines (JTLs), and simple digital circuits such as half-adder (HA) have been designed, fabricated and tested using either conventional (RSFQ) or energy-efficient (ERSFQ) approach. The ERSFQ HA cells with bias inductors fabricated in two planarized layers were shown to function with the operational margins of +/-22%.
We report on technique and results for superconductor electronics fabrication process, featuring customizable number of planarized superconducting layers. The novel technique enhanced yield on stackable vias of our standard planarized process (RIPPLE) by eliminating the need for an additional deposition of aluminum as an etch stop in the metal-via stack. The drawback of the previous approach was the difficulty in processing aluminum using either wet or dry etch mechanisms. Here, we discuss details of the novel fabrication process flow and its realization for 4.5 kA/cm2 fabrication process with six Nb layers with two fully planarized layers. We report test results of various planarization diagnostics structures, accounting the influence of topology on Josephson junction quality, as well as yield and critical current of via stacks. We also report on inductance measurement results providing information on interlayer dielectric thickness for planarized layers; confirming a good uniformity over the wafer. Basic components of superconducting logic such as dc/SFQ, SFQ/dc converters, Josephson transmission lines (JTLs), and simple digital circuits such as half-adder (HA) have been designed, fabricated and tested using either conventional (RSFQ) or energy-efficient (ERSFQ) approach. The ERSFQ HA cells with bias inductors fabricated in two planarized layers were shown to function with the operational margins of +/-22%.
To improve the operating speed and density of Nb single-flux-quantum integrated circuits, we developed an advanced fabrication process based on NEC's standard process. We fabricated planarized six-Nb-layer circuit structures using this advanced process. This new structure has four Nb wiring layers for greater design flexibility. To shield the magnetic field produced by the DC bias current, the DC bias power supply layer was placed under the groundplane. The critical current density of the Josephson junction was 10 kA/cm/sup 2/. We fabricated and tested more than 10 wafers and demonstrated that the six-layer circuits were successfully planarized. We also confirmed insulation between each Nb layer and the reliability of superconducting contacts. This planarization did not significantly degrade the junction characteristics. We measured small spreads in the critical current of less than 2%. These results demonstrated the effectiveness of this advanced process based on mechanical-polishing planarization.
Development of 15kA/cm2 Fabrication Process for Superconducting Integrated Digital Circuits
A new fabrication process for superconducting integrated digital circuits is reported. We have developed the "SIMIT Nb04" fabrication technique for superconducting integrated circuits with Nb-based Josephson junctions based on the validated "SIMIT Nb03" process and Chemical Mechanical Planarization (CMP) technology. Seven Nb superconducting layers and one Mo resistor layer are included in the "SIMIT Nb04" process with 19 mask levels. The device structure is composed of active layers including junctions at the bottom, two passive transmission line (PTL) layers in the middle and a DC power layer at the top. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance Rsh of 3 Ω, followed by the deposition of Nb/Al-AlOx/Nb trilayer Josephson-junction with a target critical current density Jc at 15 kA/cm2. To increase the Al-AlOx barrier layer etching's repeatability, an additional barrier protection layer was applied. To accomplish high-quality planarization, we created a planarization procedure coupled with dummy filling. To assess the process dependability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and monitored. The successful manufacturing and testing of a few small-scale circuits, like our standard library cells, further attests to the viability of our fabrication process for superconducting integrated circuits.
Abstract We present SIMIT-Nb08, an eight-layer Nb-based fabrication process for double-active-layer single-flux-quantum (SFQ) digital circuits, aimed at overcoming the routing congestion and integration ‘density wall’ of planar SFQ designs. Both Nb/Al–AlO x /Nb JJ layers were designed with the same nominal critical current density of J c = 6 kA cm −2 , and the measured values were 6.15 and 6.26 kA cm −2 for the lower and upper JJ layers, respectively. This architecture incorporates a dual-ground-plane structure to reduce interlayer electromagnetic coupling and shield stray magnetic flux generated by bias lines. A stop-on-metal chemical mechanical polishing module was implemented to provide a controlled dielectric thickness and a planar surface for upper-layer device fabrication. We validate a double-layer SFQ logic cell library with wide DC bias margins on both layers, and demonstrate ultra-high-speed dynamic operation via a toggle flip-flop-based frequency-divider test exceeding 100 GHz. In addition, the process and cross-layer interconnect reliability are demonstrated by functional operation of a cross-layer one-bit full adder and an eight-bit shift register (SR), where the SR exhibits an effective junction-density improvement of ∼4× over typical single-layer implementations. Post-route benchmarking on a 320-cell SR indicates that SIMIT-Nb08 delivers substantial improvements in power, performance, and area, including a 32.2% reduction in area, a 25.0% increase in maximum operating frequency ( f max ), and a 65.3% reduction in estimated power compared with SIMIT-Nb03 (29.9%, 6.3%, and 62.5%, respectively, compared with SIMIT-Nb04), indicating its potential for routing-constrained SFQ digital circuits.
We developed a Nb 4-layer process for fabricating superconducting integrated circuits that involves using caldera planarization to increase the flexibility and reliability of the fabrication process. We call this process the planarized high-speed standard process (PHSTP). Planarization enables us to flexibly adjust most of the Nb and SiO2 film thicknesses; we can select reduced film thicknesses to obtain larger mutual coupling depending on the application. It also reduces the risk of intra-layer shorts due to etching residues at the step-edge regions. We describe the detailed process flows of the planarization for the Josephson junction layer and the evaluation of devices fabricated with PHSTP. The results indicated no short defects or degradation in junction characteristics and good agreement between designed and measured inductances and resistances. We also developed single-flux-quantum (SFQ) and adiabatic quantum-flux-parametron (AQFP) logic cell libraries and tested circuits fabricated with PHSTP. We found that the designed circuits operated correctly. The SFQ shift-registers fabricated using PHSTP showed a high yield. Numerical simulation results indicate that the AQFP gates with increased mutual coupling by the planarized layer structure increase the maximum interconnect length between gates.
We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. The minimum feature size of resistors and inductors in the process is 250 nm. We present data on the mutual inductance of Nb stripline and microstrip inductors with linewidth and spacing from 250 nm to 1 μm made on the same or adjacent Nb layers, as well as the data on the linewidth and resistance uniformity.
Using a fully automated cryogenic wafer prober, we measured superconductor fabrication process control monitors and simple integrated circuits on 200-mm wafers at 4.4 K, including SQIF-based magnetic field sensors, SQUID-based circuits for measuring inductors, Nb/Al-AlOx/Nb Josephson junctions, test structures for measuring critical current of superconducting wires and vias, resistors, etc., to demonstrate the feasibility of using the system for characterizing niobium superconducting devices and integrated circuits on a wafer scale. Data on the wafer-scale distributions of the residual magnetic field, junction tunnel resistance, energy gap, inductance of multiple Nb layers, and critical currents of interlayer vias are presented. A comparison with existing models is made. The wafers were fabricated in the SFQ5ee process, the fully planarized process with eight niobium layers and a layer of kinetic inductors, developed for superconductor electronics at MIT Lincoln Laboratory, Lexington, MA, USA. The cryogenic wafer prober was developed at HPD/FormFactor, Inc., Boulder, CO, USA.