Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Transactions on Applied Superconductivity

Performance of Josephson array systems related to fabrication techniques and design

F. Muller, J. Kohlmann, Franz X. Hebrank, Thomas Weimann, Henning Wolf, J. Niemeyer

Published Jun 1, 1995• 23 citations
Publisher

Abstract

Arrays of Nb/Al/sub 2/O/sub 3//Nb Josephson tunnel junctions show dc characteristics of high quality when the trilayer is deposited direct on polished Si wafers. Underlayers such as rf-sputtered SiO/sub 2/, can considerably degrade the junction parameters. These results suggest that voltage standard chips should be produced with a cover instead of a groundplane. First results of attenuation measurements on such circuits are presented and discussed. Furthermore, a new and more simple fabrication process without a window-insulating layer and only two photolithographic steps is presented. Arrays of several thousands of junctions showed no problems of any kind with trapped flux.>

DOI
10.1109/77.403199

Related papers

Improved 1 V and 10 V Josephson voltage standard arrays

J. Kohlmann, F. Muller, P. Gutmann +5 more

1 V and 10 V Josephson voltage standard arrays are fabricated on the basis of an improved design, using a modified technology. The Nb/Al/sub 2/O/sub 3//Nb trilayer is deposited directly on the Si wafer. The edges of the base electrodes are insulated by an anodization process. The maximum step voltage increases linearly with the external microwave voltage. Switching between different voltage levels is possible by simple switching of the dc voltage bias. A laboratory-made, oversized circular waveguide reduces the attenuation of the experimental set-up.

IEEE Transactions on Applied Superconductivity•Jun 1, 1997•26 citations

A simple and robust niobium Josephson junction integrated circuit process

Andrew T. Barfknecht, Rich Ruby, H.L. Ko

A simple and robust process for fabricating low-T/sub c/ Josephson junction integrated circuits has been developed. The process is designed around the Nb/Al/sub 2/O/sub 3/-Al/Nb trilayer, and utilized nine masking steps to form two separate levels of trilayer Josephson junctions, as well as resistors, capacitors, and transmission lines. Materials used for interlayer dielectrics and passivation layers are silicon dioxide and silicon nitride formed by plasma-enhanced chemical vapor deposition (PECVD). The PECVD equipment yields a high deposition rate at moderate substrate temperatures. No degradation of the junction characteristics due to these depositions is seen. The measured loss tangent of this dielectric at 10 GHz using a parallel plate technique is 4.44*10/sup -4/. The dielectric constant of this material is 5.1 in the range of 50 to 400 GHz, measured using an on-chip resonator capacitively coupled to a single shunted Josephson junction. The physical quality of the oxide has been investigated using a variety of tests and has proven to be excellent. A variety of simple circuits using this process technology have been fabricated and tested. More complex circuits are currently under development.

IEEE Transactions on Magnetics•Mar 1, 1991•35 citations

Fabrication And Characterization Of High-Quality Nb/Al-AlO$_x$/Nb Cross-Type Josephson Tunnel Junctions Utilising CMP-based Planarisation Techniques

Alexander Stoll, Andreas Reifenberger, Daniel Hengstler +2 more

Josephson tunnel junctions (JJs) are the fundamental building blocks of today's most advanced superconducting electronic components, such as qubits and superconducting quantum interference devices (SQUIDs). Given the ongoing demand for scalability of these devices on the wafer-scale, it is crucial to control the fabrication process as precisely as possible to ensure uniform quality and reproducibility. Today, window-type JJs are often used in the production of DC SQUIDs and while they are reliable and reproducible, they suffer from alignment inaccuracies caused by photolithography and unavoidable parasitic capacitances, thus limiting the energy sensitivity of DC SQUIDs. These problems can be circumvented by producing JJs with cross-type geometry, which allows for smaller junction areas and eliminates parasitic capacitances. Here we discuss the fabrication of Nb/Al-AlOx/Nb-based cross-type JJs, where the trilayer is embedded in sputter-deposited SiO$_2$ to allow for planarisation of the structures and to ensure the reliable insulation of the sidewalls of the bottom electrode. Instead of lift-off processes that require a lot of time and potentially leave unwanted wings along the edges of microstructures behind that might compromise subsequent layers, we use chemical-mechanical polishing (CMP) for the removal of excess SiO$_2$. This is not only much faster, but produces smooth and uniform surfaces, which in turn effectively improves the reliability of our JJ production process resulting in a high yield of over $90\,\%$ on wafer-scale. In addition, we discuss the influence of fabrication details on the quality and electrical properties of our JJs with different junction areas down to $1\,\mathrm{μm} \times 1\,\mathrm{μm}$ distributed across the wafer and extract the junction specific quality parameters from their IV-characteristics and their Fraunhofer patterns.

arXiv:2609.08569•Aug 26, 2026•0 citations

A SIMPLE AND ROBUST NIOBIUM JOSEPHSON JUNCTION INTEGRATED CIRCUIT PROCESS A.T. Barflcnecht. R.C. Rubyt and H. Kot Conductus, Inc.

W. Maude Ave

A simple and robust process for fabricating low-Tc Josephson junction integrated circuits has been developed. The process is designed around the Nb/A1203-Al/Nb trilayer, and utilizes nine masking steps to form two separate levels of trilayer Josephson junctions, as well as resistors, capacitors, and transmission lines. Materials used for interlayer dielectrics and passivation layers are silicon dioxide and silicon nitride formed by Plasma Enhanced Chemical Vapor Deposition (PECVD). The PECVD equipment that we use yields a high deposition rate at moderate substrate temperatures. We see no degradation of the junction characteristics due to these depositions. The measured loss tangent of this dielectric at 10 GHz using a parallel plate technique is 4.44 x 10-4. The dielectric constant of this material is 5.1 in the range of 50 to 400 GHz, measured using an on-chip resonator capacitively coupled to a single shunted Josephson junction. The physical quality of the oxide has been investigated using a variety of tests and has proven to be excellent. We have successfully fabricated and tested a variety of simple circuits using this process technology. Much more complex circuits are currently under development (Fig. 1).

•Jan 1, 1991•0 citations

High-quality sub-micron Nb trilayer tunnel junctions for a 100 GHz SIS receiver

A. Hodge Worsham, D. E. Prober, J.H. Kang +2 more

A modified SNIP process was used to fabricate high-quality 0.5, 2, and 4 mu m/sup 2/ small-area Nb/AlO/sub x//Nb trilayer tunnel junctions with current densities as large as 5000 A/cm/sup 2/. The average junction quality factors for the junctions at 4.4 K were V/sub m/(2 mV)=39 mV for J/sub c/=3000 A/cm/sup 2/ and V/sub m/ (2 mV)=27 mV for J/sub c/=5000 A/cm/sup 2/. The best values of V/sub m/ obtained were 50 mV for J/sub c/=3000 A/cm/sup 2/ and 41 mV for J/sub c/=5000 A/cm/sup 2/. These devices were designed and fabricated for use in a W-band mixer receiver. The substrate was 50- mu m-thick fused or crystal quartz. Special methods were developed for handling such thin insulating substrates and patterning films. The fabrication process was self-aligned and used SiO/sub 2/ instead of anodized Nb as the thick insulator. SiO/sub 2/ isolated the junction area and defined the opening for contact to the Nb wiring layer. The authors have fabricated series arrays of up to 12 junctions, with individual junction areas of 0.5 mu m/sup 2/. The array I-V quality was not degraded compared to that of an individual junction.

IEEE Transactions on Magnetics•Mar 1, 1991•17 citations

Fabrication and performance of all NbN Josephson junction circuits

Masoud Radparvar, M. Berry, R.E. Drake +3 more

A novel process suitable for fabricating superconducting circuitry based on the all refractory material NbN is described. In this process, an in-situ trilayer film composed of NbN/MgO/NbN is used to fabricate Josephson tunnel junctions. Reactive ion etching processes are used to delineate devices and pattern insulators and metallizations. Fabricated junctions have yielded good tunneling characteristics with reasonable current density uniformity and reproducibility. Devices with gap voltages close to 5mV have been achieved for high quality junctions. In addition to the trilayer, there are two wiring layers, two resistor depositions, and two insulation layers, constituting a full NbN based fabrication technology. Using this process, we fabricated and successfully tested thin film DC SQUID and time domain reflectometer (TDR) circuits. Preliminary measurements suggest that the critical temperature of these circuits is well within the operating temperature of commercial two-stage closed cycle refrigerators.

IEEE Transactions on Magnetics•Mar 1, 1987•32 citations
Arrays of Nb/Al/sub 2/O/sub 3//Nb Josephson tunnel junctions show dc characteristics of high quality when the trilayer is deposited direct on polished Si wafers. Underlayers such as rf-sputtered SiO/sub 2/, can considerably degrade the junction parameters. These results suggest that voltage standard chips should be produced with a cover instead of a groundplane. First results of attenuation measurements on such circuits are presented and discussed. Furthermore, a new and more simple fabrication process without a window-insulating layer and only two photolithographic steps is presented. Arrays of several thousands of junctions showed no problems of any kind with trapped flux.>
1 V and 10 V Josephson voltage standard arrays are fabricated on the basis of an improved design, using a modified technology. The Nb/Al/sub 2/O/sub 3//Nb trilayer is deposited directly on the Si wafer. The edges of the base electrodes are insulated by an anodization process. The maximum step voltage increases linearly with the external microwave voltage. Switching between different voltage levels is possible by simple switching of the dc voltage bias. A laboratory-made, oversized circular waveguide reduces the attenuation of the experimental set-up.
A simple and robust process for fabricating low-T/sub c/ Josephson junction integrated circuits has been developed. The process is designed around the Nb/Al/sub 2/O/sub 3/-Al/Nb trilayer, and utilized nine masking steps to form two separate levels of trilayer Josephson junctions, as well as resistors, capacitors, and transmission lines. Materials used for interlayer dielectrics and passivation layers are silicon dioxide and silicon nitride formed by plasma-enhanced chemical vapor deposition (PECVD). The PECVD equipment yields a high deposition rate at moderate substrate temperatures. No degradation of the junction characteristics due to these depositions is seen. The measured loss tangent of this dielectric at 10 GHz using a parallel plate technique is 4.44*10/sup -4/. The dielectric constant of this material is 5.1 in the range of 50 to 400 GHz, measured using an on-chip resonator capacitively coupled to a single shunted Josephson junction. The physical quality of the oxide has been investigated using a variety of tests and has proven to be excellent. A variety of simple circuits using this process technology have been fabricated and tested. More complex circuits are currently under development.
Fabrication And Characterization Of High-Quality Nb/Al-AlOx_xx​/Nb Cross-Type Josephson Tunnel Junctions Utilising CMP-based Planarisation Techniques
Josephson tunnel junctions (JJs) are the fundamental building blocks of today's most advanced superconducting electronic components, such as qubits and superconducting quantum interference devices (SQUIDs). Given the ongoing demand for scalability of these devices on the wafer-scale, it is crucial to control the fabrication process as precisely as possible to ensure uniform quality and reproducibility. Today, window-type JJs are often used in the production of DC SQUIDs and while they are reliable and reproducible, they suffer from alignment inaccuracies caused by photolithography and unavoidable parasitic capacitances, thus limiting the energy sensitivity of DC SQUIDs. These problems can be circumvented by producing JJs with cross-type geometry, which allows for smaller junction areas and eliminates parasitic capacitances. Here we discuss the fabrication of Nb/Al-AlOx/Nb-based cross-type JJs, where the trilayer is embedded in sputter-deposited SiO2_22​ to allow for planarisation of the structures and to ensure the reliable insulation of the sidewalls of the bottom electrode. Instead of lift-off processes that require a lot of time and potentially leave unwanted wings along the edges of microstructures behind that might compromise subsequent layers, we use chemical-mechanical polishing (CMP) for the removal of excess SiO2_22​. This is not only much faster, but produces smooth and uniform surfaces, which in turn effectively improves the reliability of our JJ production process resulting in a high yield of over 90 %90\,\%90% on wafer-scale. In addition, we discuss the influence of fabrication details on the quality and electrical properties of our JJs with different junction areas down to 1 μm×1 μm1\,\mathrm{μm} \times 1\,\mathrm{μm}1μm×1μm distributed across the wafer and extract the junction specific quality parameters from their IV-characteristics and their Fraunhofer patterns.
A simple and robust process for fabricating low-Tc Josephson junction integrated circuits has been developed. The process is designed around the Nb/A1203-Al/Nb trilayer, and utilizes nine masking steps to form two separate levels of trilayer Josephson junctions, as well as resistors, capacitors, and transmission lines. Materials used for interlayer dielectrics and passivation layers are silicon dioxide and silicon nitride formed by Plasma Enhanced Chemical Vapor Deposition (PECVD). The PECVD equipment that we use yields a high deposition rate at moderate substrate temperatures. We see no degradation of the junction characteristics due to these depositions. The measured loss tangent of this dielectric at 10 GHz using a parallel plate technique is 4.44 x 10-4. The dielectric constant of this material is 5.1 in the range of 50 to 400 GHz, measured using an on-chip resonator capacitively coupled to a single shunted Josephson junction. The physical quality of the oxide has been investigated using a variety of tests and has proven to be excellent. We have successfully fabricated and tested a variety of simple circuits using this process technology. Much more complex circuits are currently under development (Fig. 1).
A modified SNIP process was used to fabricate high-quality 0.5, 2, and 4 mu m/sup 2/ small-area Nb/AlO/sub x//Nb trilayer tunnel junctions with current densities as large as 5000 A/cm/sup 2/. The average junction quality factors for the junctions at 4.4 K were V/sub m/(2 mV)=39 mV for J/sub c/=3000 A/cm/sup 2/ and V/sub m/ (2 mV)=27 mV for J/sub c/=5000 A/cm/sup 2/. The best values of V/sub m/ obtained were 50 mV for J/sub c/=3000 A/cm/sup 2/ and 41 mV for J/sub c/=5000 A/cm/sup 2/. These devices were designed and fabricated for use in a W-band mixer receiver. The substrate was 50- mu m-thick fused or crystal quartz. Special methods were developed for handling such thin insulating substrates and patterning films. The fabrication process was self-aligned and used SiO/sub 2/ instead of anodized Nb as the thick insulator. SiO/sub 2/ isolated the junction area and defined the opening for contact to the Nb wiring layer. The authors have fabricated series arrays of up to 12 junctions, with individual junction areas of 0.5 mu m/sup 2/. The array I-V quality was not degraded compared to that of an individual junction.
A novel process suitable for fabricating superconducting circuitry based on the all refractory material NbN is described. In this process, an in-situ trilayer film composed of NbN/MgO/NbN is used to fabricate Josephson tunnel junctions. Reactive ion etching processes are used to delineate devices and pattern insulators and metallizations. Fabricated junctions have yielded good tunneling characteristics with reasonable current density uniformity and reproducibility. Devices with gap voltages close to 5mV have been achieved for high quality junctions. In addition to the trilayer, there are two wiring layers, two resistor depositions, and two insulation layers, constituting a full NbN based fabrication technology. Using this process, we fabricated and successfully tested thin film DC SQUID and time domain reflectometer (TDR) circuits. Preliminary measurements suggest that the critical temperature of these circuits is well within the operating temperature of commercial two-stage closed cycle refrigerators.