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arXiv:2006.16862 · Applied Physics Letters

Coherent superconducting qubits from a subtractive junction fabrication process

Alexander Stehli, Jan David Brehm, Tim Wolz, Paul Baity, Sergey Danilin, Valentino Seferai, Hannes Rotzinger, Alexey V. Ustinov, Martin Weides

Published Sep 21, 2020• 34 citations
arXivHTMLPDF

Abstract

Josephson tunnel junctions are the centerpiece of almost any superconducting electronic circuit, including qubits. Typically, the junctions for qubits are fabricated using shadow evaporation techniques to reduce dielectric loss contributions from the superconducting film interfaces. In recent years, however, sub-micrometer scale overlap junctions have started to attract attention. Compared to shadow mask techniques, neither an angle dependent deposition nor free-standing bridges or overlaps are needed, which are significant limitations for wafer-scale processing. This comes at the cost of breaking the vacuum during fabrication, but simplifies integration in multi-layered circuits and implementation of vastly different junction sizes and enables fabrication on a larger scale in an industrially standardized process. In this work, we demonstrate the feasibility of a subtractive process for the fabrication of overlap junctions. In an array of test contacts, we find low aging of the average normal state resistance of only 1.6% over 6 months. We evaluate the coherence properties of the junctions by employing them in superconducting transmon qubits. In time domain experiments, we find that both, the qubit life- and coherence time of our best device, are, on average, greater than 20 μs. Finally, we discuss potential improvements to our technique. This work paves the way toward a more standardized process flow with advanced materials and growth processes, and constitutes an important step for the large scale fabrication of superconducting quantum circuits.

DOI
10.1063/5.0023533

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Josephson tunnel junctions are the centerpiece of almost any superconducting electronic circuit, including qubits. Typically, the junctions for qubits are fabricated using shadow evaporation techniques to reduce dielectric loss contributions from the superconducting film interfaces. In recent years, however, sub-micrometer scale overlap junctions have started to attract attention. Compared to shadow mask techniques, neither an angle dependent deposition nor free-standing bridges or overlaps are needed, which are significant limitations for wafer-scale processing. This comes at the cost of breaking the vacuum during fabrication, but simplifies integration in multi-layered circuits and implementation of vastly different junction sizes and enables fabrication on a larger scale in an industrially standardized process. In this work, we demonstrate the feasibility of a subtractive process for the fabrication of overlap junctions. In an array of test contacts, we find low aging of the average normal state resistance of only 1.6% over 6 months. We evaluate the coherence properties of the junctions by employing them in superconducting transmon qubits. In time domain experiments, we find that both, the qubit life- and coherence time of our best device, are, on average, greater than 20 μs. Finally, we discuss potential improvements to our technique. This work paves the way toward a more standardized process flow with advanced materials and growth processes, and constitutes an important step for the large scale fabrication of superconducting quantum circuits.
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T1 relaxation times averaging above 50 μs (Q>1.5×106). Current shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. This eliminates a key bottleneck in manufacturing superconducting qubits by reducing the fabrication time and cost. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty 0.5×0.5-cm2 chips, with junction areas ranging between 0.01 and 0.16 μm2. The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4% and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7%–2.5%. We show that 60%–70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.
Fabrication of sub-micron Josephson junctions is demonstrated using standard processing techniques for high-coherence, superconducting qubits. These junctions are made in two separate lithography steps with normal-angle evaporation. Most significantly, this work demonstrates that it is possible to achieve high coherence with junctions formed on aluminum surfaces cleaned in situ with Ar milling before the junction oxidation. This method eliminates the angle-dependent shadow masks typically used for small junctions. Therefore, this is conducive to the implementation of typical methods for improving margins and yield using conventional CMOS processing. The current method uses electron-beam lithography and an additive process to define the top and bottom electrodes. Extension of this work to optical lithography and subtractive processes is discussed.
The performance of superconducting electronic devices such as superconducting quantum bits (qubits) and superconducting quantum interference devices (SQUIDs) strongly relies on high-quality Josephson junctions (JJ) and their integration into surrounding circuit elements. Therefore, a corresponding fabrication technology should allow for the fabrication of all required elements including the JJs, inductances, capacitances and waveguides. For a long time, shadow evaporation technique was the state of the art for the implementation of sub-μ m sized JJs based on aluminum for qubits of high coherence times. Although, the use of a single lithographic step represents a major advantage of this technique. However, shadowing effects limit sample size, device complexity, and thus scalability of the circuitry. To overcome these limitations and to meet the demands of next generation scalable quantum circuits, in this work we introduce our cross -type JJ aluminum technology, where JJs are defined by the overlap of two narrow perpendicular stripes. We discuss the technological challenges, with a focus on our newly developed dry etching process for patterning of the aluminum thin film. Compared to a lift-off based process, this advanced wafer-scale fabrication technology offers a high integration density and the required design flexibility. We will present first results on cross -type aluminum JJs.
Abstract As the superconducting qubit platform matures towards ever-larger scales in the race towards a practical quantum computer, limitations due to qubit inhomogeneity through lack of process control become apparent. To benefit from the advanced process control in industry-scale CMOS fabrication facilities, different processing methods will be required. In particular, the double-angle evaporation and lift-off techniques used for current, state-of-the-art superconducting qubits are generally incompatible with modern-day manufacturable processes. Here, we demonstrate a fully CMOS compatible qubit fabrication method, and show results from overlap Josephson junction devices with long coherence and relaxation times, on par with the state-of-the-art. We experimentally verify that Argon milling—the critical step during junction fabrication—and a subtractive-etch process nevertheless result in qubits with average qubit energy relaxation times T 1 reaching 70 µs, with maximum values exceeding 100 µs. Furthermore, we show that our results are still limited by surface losses and not, crucially, by junction losses. The presented fabrication process, therefore, heralds an important milestone towards a manufacturable 300 mm CMOS process for high-coherence superconducting qubits and has the potential to advance the scaling of superconducting device architectures.
Josephson tunnel junctions represent a key element in superconducting electronics and quantum circuits. For many years, shadow evaporation by means of Dolan-type bridges has been the state-of-the-art for deep sub- micrometer sized structures. Increasing demand in the number of Josephson junctions, e.g. in qubit circuits and travelling wave parametric amplifiers, requests for a wafer-scale fabrication process with precise control of junction parameters and have led to an advanced lift-off technique called Manhattan-type junction technology in recent years. Herein, we report on the development of a 100 mm wafer-scale fabrication technology for deep sub-micrometer sized Al Josephson junctions with linear dimensions down to 180 nm. The critical currentICof the junctions ranges from about 10 to 120 nA scaling with their linear dimensions. Low temperature transport measurements as well as room-temperature characterization has been used forICand process homogeneity determination of series arrays of up to 50 Josephson junctions. We discuss technology parameters such as yield, on-chip and on-wafer reproducibility of the junction's critical currents as well as main process limitations. Moreover, we present experimental results on the characterization of first transmon-type qubits fabricated using this technology.
Superconducting qubits in today's quantum processing units are typically fabricated with angle-evaporated aluminum--aluminum-oxide--aluminum Josephson junctions. However, there is an urgent need to overcome the limited reproducibility of this approach when scaling up the number of qubits and junctions. Fabrication methods based on subtractive patterning of superconductor--insulator--superconductor trilayers, used for more classical large-scale Josephson junction circuits, could provide the solution but they in turn often suffer from lossy dielectrics incompatible with high qubit coherence. In this work, we utilize native aluminum oxide as a sidewall passivation layer for junctions based on aluminum--aluminum-oxide--niobium trilayers, and use such junctions in qubits. We design the fabrication process such that the few-nanometer-thin native oxide is not exposed to oxide removal steps that could increase its defect density or hinder its ability to prevent shorting between the leads of the junction. With these junctions, we design and fabricate transmon-like qubits and measure time-averaged coherence times up to 30 μμμs at a qubit frequency of 5 GHz, corresponding to a qubit quality factor of one million. Our process uses subtractive patterning and optical lithography on wafer scale, enabling high throughput in patterning. This approach provides a scalable path toward fabrication of superconducting qubits on industry-standard platforms.