Path toward manufacturable superconducting qubits with relaxation times exceeding 0.1 ms
Jeroen Verjauw, R. Acharya, Jacques Van Damme, Ts. Ivanov, Daniel Pérez Lozano, Fahd A. Mohiyaddin, Danny Wan, Julien Jussot, A. M. Vadiraj, Massimo Mongillo, Marc Heyns, Iuliana P. Radu, B. Govoreanu, Anton Potočnik
Abstract As the superconducting qubit platform matures towards ever-larger scales in the race towards a practical quantum computer, limitations due to qubit inhomogeneity through lack of process control become apparent. To benefit from the advanced process control in industry-scale CMOS fabrication facilities, different processing methods will be required. In particular, the double-angle evaporation and lift-off techniques used for current, state-of-the-art superconducting qubits are generally incompatible with modern-day manufacturable processes. Here, we demonstrate a fully CMOS compatible qubit fabrication method, and show results from overlap Josephson junction devices with long coherence and relaxation times, on par with the state-of-the-art. We experimentally verify that Argon milling—the critical step during junction fabrication—and a subtractive-etch process nevertheless result in qubits with average qubit energy relaxation times T 1 reaching 70 µs, with maximum values exceeding 100 µs. Furthermore, we show that our results are still limited by surface losses and not, crucially, by junction losses. The presented fabrication process, therefore, heralds an important milestone towards a manufacturable 300 mm CMOS process for high-coherence superconducting qubits and has the potential to advance the scaling of superconducting device architectures.
Abstract As the superconducting qubit platform matures towards ever-larger scales in the race towards a practical quantum computer, limitations due to qubit inhomogeneity through lack of process control become apparent. To benefit from the advanced process control in industry-scale CMOS fabrication facilities, different processing methods will be required. In particular, the double-angle evaporation and lift-off techniques used for current, state-of-the-art superconducting qubits are generally incompatible with modern-day manufacturable processes. Here, we demonstrate a fully CMOS compatible qubit fabrication method, and show results from overlap Josephson junction devices with long coherence and relaxation times, on par with the state-of-the-art. We experimentally verify that Argon milling—the critical step during junction fabrication—and a subtractive-etch process nevertheless result in qubits with average qubit energy relaxation times T 1 reaching 70 µs, with maximum values exceeding 100 µs. Furthermore, we show that our results are still limited by surface losses and not, crucially, by junction losses. The presented fabrication process, therefore, heralds an important milestone towards a manufacturable 300 mm CMOS process for high-coherence superconducting qubits and has the potential to advance the scaling of superconducting device architectures.
Abstract The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers 1,2 . As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical 3 . Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal–oxide–semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 μs. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing 4 . Moreover, it offers the potential for further upscaling through three-dimensional integration 5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors.
Abstract The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers1, 2. As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical3. Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal–oxide–semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 μs. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing4. Moreover, it offers the potential for further upscaling through three-dimensional integration5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors.
We present the results of an industry-grade fabrication of superconducting qubits on 200 mm wafers utilizing CMOS-established processing methods. By automated waferprober resistance measurements at room temperature, we demonstrate a Josephson junction fabrication yield of 99.7% (shorts and opens) across more than 10000 junctions and a qubit frequency prediction accuracy of 1.6%. In cryogenic characterization, we provide statistical results regarding energy relaxation times of the qubits with a median T1 of up to 100 us and individual devices consistently approaching 200 us in long-term measurements. This represents the best performance reported so far for superconducting qubits fabricated by industry-grade, wafer-level subtractive processes.
Josephson tunnel junctions are the centerpiece of almost any superconducting electronic circuit, including qubits. Typically, the junctions for qubits are fabricated using shadow evaporation techniques to reduce dielectric loss contributions from the superconducting film interfaces. In recent years, however, sub-micrometer scale overlap junctions have started to attract attention. Compared to shadow mask techniques, neither an angle dependent deposition nor free-standing bridges or overlaps are needed, which are significant limitations for wafer-scale processing. This comes at the cost of breaking the vacuum during fabrication, but simplifies integration in multi-layered circuits and implementation of vastly different junction sizes and enables fabrication on a larger scale in an industrially standardized process. In this work, we demonstrate the feasibility of a subtractive process for the fabrication of overlap junctions. In an array of test contacts, we find low aging of the average normal state resistance of only 1.6% over 6 months. We evaluate the coherence properties of the junctions by employing them in superconducting transmon qubits. In time domain experiments, we find that both, the qubit life- and coherence time of our best device, are, on average, greater than 20 μs. Finally, we discuss potential improvements to our technique. This work paves the way toward a more standardized process flow with advanced materials and growth processes, and constitutes an important step for the large scale fabrication of superconducting quantum circuits.
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T1 relaxation times averaging above 50 μs (Q>1.5×106). Current shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. This eliminates a key bottleneck in manufacturing superconducting qubits by reducing the fabrication time and cost. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty 0.5×0.5-cm2 chips, with junction areas ranging between 0.01 and 0.16 μm2. The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4% and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7%–2.5%. We show that 60%–70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.
Fabrication of sub-micron Josephson junctions is demonstrated using standard processing techniques for high-coherence, superconducting qubits. These junctions are made in two separate lithography steps with normal-angle evaporation. Most significantly, this work demonstrates that it is possible to achieve high coherence with junctions formed on aluminum surfaces cleaned in situ with Ar milling before the junction oxidation. This method eliminates the angle-dependent shadow masks typically used for small junctions. Therefore, this is conducive to the implementation of typical methods for improving margins and yield using conventional CMOS processing. The current method uses electron-beam lithography and an additive process to define the top and bottom electrodes. Extension of this work to optical lithography and subtractive processes is discussed.