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arXiv:2507.17005 · Applied Physics Reviews

On-chip stencil lithography for superconducting qubits

Roudy Hanna, Soeren Ihssen, Simon Geisert, Umut Koçak, Matteo Arfini, Albert Hertel, Thomas J. Smart, Michael Schleenvoigt, Tobias Schmitt, Joscha Domnick, Kaycee Underwood, Abdur Rehman Jalil, Jin Hee Bae, Benjamin Bennemann, Mathieu Féchant, M. E. Field, Martin Spiecker, Nicolas Zapata, Christian Dickel, Erwin Berenschot, Niels R. Tas, Gary Alexander Steele, Detlev Grützmacher, Ioan M. Pop, Peter Schüffelgen

Published Apr 6, 2026• 0 citations
arXivHTMLPDF

Abstract

Improvements in circuit design and, more recently, in materials and surface cleaning have contributed to a rapid development of coherent superconducting qubits. However, organic resists commonly used for shadow evaporation of Josephson junctions (JJs) pose limitations due to residual contamination, poor thermal stability, and compatibility under typical surface-cleaning conditions. To provide an alternative, we developed an inorganic SiO2/Si3N4 on-chip stencil lithography mask for JJ fabrication. The stencil mask is resilient to aggressive cleaning agents and it withstands high temperatures up to 1200 °C, thereby opening new avenues for JJ material exploration and interface optimization. To validate the concept, we performed shadow evaporation of Al-based transmon qubits followed by stencil mask liftoff using vapor hydrofluoric acid, which selectively etches SiO2. We demonstrate an average T1≈75±11 μs over a 200 MHz frequency range across multiple cooldowns for one device, and T1≈44±8 μs for a second device. These results confirm the compatibility of stencil lithography with state-of-the-art superconducting quantum devices and motivate further investigations into materials engineering, film deposition, and surface cleaning techniques.

DOI
10.1063/5.0307532

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Improvements in circuit design and, more recently, in materials and surface cleaning have contributed to a rapid development of coherent superconducting qubits. However, organic resists commonly used for shadow evaporation of Josephson junctions (JJs) pose limitations due to residual contamination, poor thermal stability, and compatibility under typical surface-cleaning conditions. To provide an alternative, we developed an inorganic SiO2/Si3N4 on-chip stencil lithography mask for JJ fabrication. The stencil mask is resilient to aggressive cleaning agents and it withstands high temperatures up to 1200 °C, thereby opening new avenues for JJ material exploration and interface optimization. To validate the concept, we performed shadow evaporation of Al-based transmon qubits followed by stencil mask liftoff using vapor hydrofluoric acid, which selectively etches SiO2. We demonstrate an average T1≈75±11 μs over a 200 MHz frequency range across multiple cooldowns for one device, and T1≈44±8 μs for a second device. These results confirm the compatibility of stencil lithography with state-of-the-art superconducting quantum devices and motivate further investigations into materials engineering, film deposition, and surface cleaning techniques.
Superconducting qubit fabrication innovations continue to be explored to achieve higher performance. Despite improvements to base layer fabrication and processing, resist-based Josephson junction (JJ) schemes have largely remained unchanged. The polymer mask during deposition causes chemical contamination and limits in situ and ex situ surface preparation, junction materials, and scalability. Here, we demonstrate a resist-free approach to junction fabrication based on etched silicon trenches that is CMOS compatible and easily integrated into existing innovations in qubit base layer fabrication and chemical processing. We fabricate Al-AlOx-Al JJs and qubits using this method, measuring median energy relaxation times up to 184 microseconds. We find minimal contamination at the substrate-metal interface and fluctuations of energy relaxation on a 35 hour timescale that are narrow and normally distributed. The method widens the process window for substrate preparation and new materials platforms.
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Josephson tunnel junctions are the centerpiece of almost any superconducting electronic circuit, including qubits. Typically, the junctions for qubits are fabricated using shadow evaporation techniques to reduce dielectric loss contributions from the superconducting film interfaces. In recent years, however, sub-micrometer scale overlap junctions have started to attract attention. Compared to shadow mask techniques, neither an angle dependent deposition nor free-standing bridges or overlaps are needed, which are significant limitations for wafer-scale processing. This comes at the cost of breaking the vacuum during fabrication, but simplifies integration in multi-layered circuits and implementation of vastly different junction sizes and enables fabrication on a larger scale in an industrially standardized process. In this work, we demonstrate the feasibility of a subtractive process for the fabrication of overlap junctions. In an array of test contacts, we find low aging of the average normal state resistance of only 1.6% over 6 months. We evaluate the coherence properties of the junctions by employing them in superconducting transmon qubits. In time domain experiments, we find that both, the qubit life- and coherence time of our best device, are, on average, greater than 20 μs. Finally, we discuss potential improvements to our technique. This work paves the way toward a more standardized process flow with advanced materials and growth processes, and constitutes an important step for the large scale fabrication of superconducting quantum circuits.
Nanofabrication techniques for superconducting qubits rely on resist-based masks patterned by electron-beam or optical lithography. We have developed an alternative nanofabrication technique based on free-standing silicon shadow masks fabricated from silicon-on-insulator wafers. These silicon shadow masks not only eliminate organic residues associated with resist-based lithography, but also provide a pathway to better understand and control surface-dielectric losses in superconducting qubits by decoupling mask fabrication from substrate preparation. We have successfully fabricated aluminum 3D transmon superconducting qubits with these shadow masks and found coherence quality factors comparable to those fabricated with standard techniques.
The performance of superconducting electronic devices such as superconducting quantum bits (qubits) and superconducting quantum interference devices (SQUIDs) strongly relies on high-quality Josephson junctions (JJ) and their integration into surrounding circuit elements. Therefore, a corresponding fabrication technology should allow for the fabrication of all required elements including the JJs, inductances, capacitances and waveguides. For a long time, shadow evaporation technique was the state of the art for the implementation of sub-μ m sized JJs based on aluminum for qubits of high coherence times. Although, the use of a single lithographic step represents a major advantage of this technique. However, shadowing effects limit sample size, device complexity, and thus scalability of the circuitry. To overcome these limitations and to meet the demands of next generation scalable quantum circuits, in this work we introduce our cross -type JJ aluminum technology, where JJs are defined by the overlap of two narrow perpendicular stripes. We discuss the technological challenges, with a focus on our newly developed dry etching process for patterning of the aluminum thin film. Compared to a lift-off based process, this advanced wafer-scale fabrication technology offers a high integration density and the required design flexibility. We will present first results on cross -type aluminum JJs.
Abstract Shadow evaporation is commonly used to micro-fabricate the key element of superconducting qubits—the Josephson junction. However, in conventional two-angle deposition circuit topology, unwanted stray Josephson junctions are created which contribute to dielectric loss. So far, this could be avoided by shorting the stray junctions with a so-called bandage layer deposited in an additional lithography step, which may further contaminate the chip surface. Here, we present an improved shadow evaporation technique allowing one to fabricate sub-micrometer-sized Josephson junctions together with bandage layers in a single lithography step. We also show that junction aging is significantly reduced when junction electrodes are passivated in an oxygen atmosphere directly after deposition.