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arXiv:2101.01453 · Superconductor Science and Technology

In-situ bandaged Josephson junctions for superconducting quantum processors

Alexander Bilmes, Alexander K Händel, Serhii Volosheniuk, Alexey Vladimirovich Ustinov, Jürgen Lisenfeld

Published Sep 27, 2021• 29 citations
arXivHTMLPDF

Abstract

Abstract Shadow evaporation is commonly used to micro-fabricate the key element of superconducting qubits—the Josephson junction. However, in conventional two-angle deposition circuit topology, unwanted stray Josephson junctions are created which contribute to dielectric loss. So far, this could be avoided by shorting the stray junctions with a so-called bandage layer deposited in an additional lithography step, which may further contaminate the chip surface. Here, we present an improved shadow evaporation technique allowing one to fabricate sub-micrometer-sized Josephson junctions together with bandage layers in a single lithography step. We also show that junction aging is significantly reduced when junction electrodes are passivated in an oxygen atmosphere directly after deposition.

DOI
10.1088/1361-6668/ac2a6d

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Abstract Shadow evaporation is commonly used to micro-fabricate the key element of superconducting qubits—the Josephson junction. However, in conventional two-angle deposition circuit topology, unwanted stray Josephson junctions are created which contribute to dielectric loss. So far, this could be avoided by shorting the stray junctions with a so-called bandage layer deposited in an additional lithography step, which may further contaminate the chip surface. Here, we present an improved shadow evaporation technique allowing one to fabricate sub-micrometer-sized Josephson junctions together with bandage layers in a single lithography step. We also show that junction aging is significantly reduced when junction electrodes are passivated in an oxygen atmosphere directly after deposition.
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T1 relaxation times averaging above 50 μs (Q>1.5×106). Current shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. This eliminates a key bottleneck in manufacturing superconducting qubits by reducing the fabrication time and cost. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty 0.5×0.5-cm2 chips, with junction areas ranging between 0.01 and 0.16 μm2. The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4% and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7%–2.5%. We show that 60%–70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.
Josephson tunnel junctions are the centerpiece of almost any superconducting electronic circuit, including qubits. Typically, the junctions for qubits are fabricated using shadow evaporation techniques to reduce dielectric loss contributions from the superconducting film interfaces. In recent years, however, sub-micrometer scale overlap junctions have started to attract attention. Compared to shadow mask techniques, neither an angle dependent deposition nor free-standing bridges or overlaps are needed, which are significant limitations for wafer-scale processing. This comes at the cost of breaking the vacuum during fabrication, but simplifies integration in multi-layered circuits and implementation of vastly different junction sizes and enables fabrication on a larger scale in an industrially standardized process. In this work, we demonstrate the feasibility of a subtractive process for the fabrication of overlap junctions. In an array of test contacts, we find low aging of the average normal state resistance of only 1.6% over 6 months. We evaluate the coherence properties of the junctions by employing them in superconducting transmon qubits. In time domain experiments, we find that both, the qubit life- and coherence time of our best device, are, on average, greater than 20 μs. Finally, we discuss potential improvements to our technique. This work paves the way toward a more standardized process flow with advanced materials and growth processes, and constitutes an important step for the large scale fabrication of superconducting quantum circuits.
Fabrication of sub-micron Josephson junctions is demonstrated using standard processing techniques for high-coherence, superconducting qubits. These junctions are made in two separate lithography steps with normal-angle evaporation. Most significantly, this work demonstrates that it is possible to achieve high coherence with junctions formed on aluminum surfaces cleaned in situ with Ar milling before the junction oxidation. This method eliminates the angle-dependent shadow masks typically used for small junctions. Therefore, this is conducive to the implementation of typical methods for improving margins and yield using conventional CMOS processing. The current method uses electron-beam lithography and an additive process to define the top and bottom electrodes. Extension of this work to optical lithography and subtractive processes is discussed.
Superconducting qubit fabrication innovations continue to be explored to achieve higher performance. Despite improvements to base layer fabrication and processing, resist-based Josephson junction (JJ) schemes have largely remained unchanged. The polymer mask during deposition causes chemical contamination and limits in situ and ex situ surface preparation, junction materials, and scalability. Here, we demonstrate a resist-free approach to junction fabrication based on etched silicon trenches that is CMOS compatible and easily integrated into existing innovations in qubit base layer fabrication and chemical processing. We fabricate Al-AlOx-Al JJs and qubits using this method, measuring median energy relaxation times up to 184 microseconds. We find minimal contamination at the substrate-metal interface and fluctuations of energy relaxation on a 35 hour timescale that are narrow and normally distributed. The method widens the process window for substrate preparation and new materials platforms.
The most commonly used physical realization of superconducting qubits for quantum circuits is a transmon. There are a number of superconducting quantum circuits applications, where Josephson junction critical current reproducibility over a chip is crucial. Here, we report on a robust chip scale Al/AlOx/AlAl/AlO_x/AlAl/AlOx​/Al junctions fabrication method due to comprehensive study of shadow evaporation and oxidation steps. We experimentally demonstrate the evidence of optimal Josephson junction electrodes thickness, deposition rate and deposition angle, which ensure minimal electrode surface and line edge roughness. The influence of oxidation method, pressure and time on critical current reproducibility is determined. With the proposed method we demonstrate Al/AlOx/AlAl/AlO_x/AlAl/AlOx​/Al junction fabrication with the critical current variation (σ/Icσ/I_cσ/Ic​) less than 3.9% (from 150×200150\times200150×200 to 150×600150\times600150×600 nm2nm^2nm2 area) and 7.7% (for 100×100100\times100100×100 nm2nm^2nm2 area) over 20×2020\times2020×20 mm2mm^2mm2 chip. Finally, we fabricate separately three 5×105\times105×10 mm2mm^2mm2 chips with 18 transmon qubits (near 4.3 GHz frequency) showing less than 1.9% frequency variation between qubit on different chips. The proposed approach and optimization criteria can be utilized for a robust wafer-scale superconducting qubit circuits fabrication.
Superconducting circuit devices require electrical interconnects between different circuit elements on the chip, for which conventional device architectures use a combination of two structural elements: \textit{airbridges} to connect non-adjacent elements in the base layer, and \textit{bandages} to connect the electrodes forming the Josephson junctions to the base layer. Bandages introduce unwanted parasitic material interfaces and increase the manufacturing complexity. Here, we overcome the limitations imposed by \emph{bandages} by establishing \textit{all} electrical interconnects with airbridges of varying size fabricated in a single step. The airbridges show a high yield and mechanical stability over a wide range of sizes from 0.5 μm0.5\,μ\mathrm{m}0.5μm to 4 μm4\,μ\mathrm{m}4μm in width and from 5 μm5\,μ\mathrm{m}5μm to 40 μm40\,μ\mathrm{m}40μm in length, and show low loss when integrated in coplanar waveguide resonators and transmon qubits. Measured relaxation times up to more than 250 μs250\,μ\mathrm{s}250μs in standard transmon geometries show that the process achieves high coherence while substantially easing and accelerating device fabrication.