Contacting Josephson Junctions via Airbridges in Superconducting Circuits
Prakiran Baidya, Momčilo Milosavljević, Murali Krishna Kurmapu, Thomas Fösel, Harshanth Ram Murugesan, Victor Kemme, Mojahed Jaber, Markus Sondermann, Christopher Eichler
quant-phSubmitted Jun 5, 2026• Announced Jun 8, 2026• 0 citations
Superconducting circuit devices require electrical interconnects between different circuit elements on the chip, for which conventional device architectures use a combination of two structural elements: \textit{airbridges} to connect non-adjacent elements in the base layer, and \textit{bandages} to connect the electrodes forming the Josephson junctions to the base layer. Bandages introduce unwanted parasitic material interfaces and increase the manufacturing complexity. Here, we overcome the limitations imposed by \emph{bandages} by establishing \textit{all} electrical interconnects with airbridges of varying size fabricated in a single step. The airbridges show a high yield and mechanical stability over a wide range of sizes from $0.5\,μ\mathrm{m}$ to $4\,μ\mathrm{m}$ in width and from $5\,μ\mathrm{m}$ to $40\,μ\mathrm{m}$ in length, and show low loss when integrated in coplanar waveguide resonators and transmon qubits. Measured relaxation times up to more than $250\,μ\mathrm{s}$ in standard transmon geometries show that the process achieves high coherence while substantially easing and accelerating device fabrication.
Superconducting circuit devices require electrical interconnects between different circuit elements on the chip, for which conventional device architectures use a combination of two structural elements: \textit{airbridges} to connect non-adjacent elements in the base layer, and \textit{bandages} to connect the electrodes forming the Josephson junctions to the base layer. Bandages introduce unwanted parasitic material interfaces and increase the manufacturing complexity. Here, we overcome the limitations imposed by \emph{bandages} by establishing \textit{all} electrical interconnects with airbridges of varying size fabricated in a single step. The airbridges show a high yield and mechanical stability over a wide range of sizes from 0.5μm to 4μm in width and from 5μm to 40μm in length, and show low loss when integrated in coplanar waveguide resonators and transmon qubits. Measured relaxation times up to more than 250μs in standard transmon geometries show that the process achieves high coherence while substantially easing and accelerating device fabrication.
Airbridges are essential for creating high-performance, low-parasitic interconnects in integrated circuits and quantum devices. Conventional multi-step fabrication methods hinder miniaturization and introduce process-related defects. We report a simplified process for fabricating nanoscale airbridges using only a single electron-beam lithography step. By optimizing a multilayer resist stack with a triple-exposure-dose scheme and a thermal reflow step, we achieve smooth, suspended metallic bridges with sub-200-nm features that exhibit robust mechanical stability. Fabricated within a gradiometric SQUID design for superconducting transmon qubits, these airbridges introduce no measurable additional loss in the relaxation time T1, while enabling a 2.5-fold enhancement of the dephasing time T2∗. This efficient method offers a practical route toward integrating high-performance three-dimensional interconnects in advanced quantum and nano-electronic devices.
In superconducting quantum devices, air bridges enable increased circuit complexity and density, and mitigate the risk of microwave loss arising from mode mixing. We implement aluminum air bridges using a simple process based on single-step electron-beam gradient exposure. The resulting bridges have sizes ranging from 20 µm to 100 µm, with a yield exceeding 99% for lengths up to 36 µm. When used to connect ground planes in coplanar waveguide resonators, the induced loss contributed to the system is negligible, corresponding to a loss per bridge less than 1.0×10−8. The bridge process is compatible with Josephson junctions and allows for the simultaneous creation of low loss bandages between superconducting layers.
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T1 relaxation times averaging above 50 μs (Q>1.5×106). Current shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. This eliminates a key bottleneck in manufacturing superconducting qubits by reducing the fabrication time and cost. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty 0.5×0.5-cm2 chips, with junction areas ranging between 0.01 and 0.16 μm2. The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4% and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7%–2.5%. We show that 60%–70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.
Grounding is crucial in coplanar superconducting circuit architectures, since chip complexity and scalability increase, asymmetries and discontinuities in the ground plane arise. These irregularities excite parasitic slotline modes, which can be coupled to qubits or other resonant modes and degrade circuit performance. Wirebonds are one of the most frequently used crossovers for grounding—also in Quanten Nano Zentrum Tirol (QNZT) — however, due to their size, they introduce large inductive losses and are not practical for large-scale chips. The small structure of airbridges causes lower inductive losses and is compatible with scalable superconducting devices because the density of airbridges can be increased simply by modifying the fabrication design. In this project, airbridges are fabricated for the first time in the QNZT using a single step grayscale electron beam lithography technique, inspired by the work of Janzen et al. [1]. To optimize the grayscale electron beam lithography process, special techniques are employed, such as delayed development [2] and 3D proximity effect correction (PEC) [3]. In addition, pure Methyl Isobutyl Ketone (MIBK) is used as the developer. The lower contrast characteristic of the positive resist is achieved by pure MIBK and delayed development, so that this technique increases the precision of the resist height after development. A high temperature reflow process is avoided, which can alter the characteristics of Josephson junctions. In addition, PEC is employed to increase the precision of the lithographic process, which is essential in low acceleration voltage Electron Beam Lithography(EBL). Eventually, we achieved a smooth arcshaped airbridge mask with over 99% yield for airbridges ranging from 45 µm to 65 µm and over 80% yield for 85 µm airbridges. These structures also demonstrated durability against dicing, ultrasonication and N2 blow-drying. Finally, two chips with CPW resonators grounded by airbridges are characterized at cryogenic temperatures.
Abstract Airbridges are essential for creating high-performance, low-parasitic interconnects in integrated circuits and quantum devices. Conventional multi-step fabrication methods hinder miniaturization and introduce process-related defects. We report a simplified process that enables the fabrication of nanoscale airbridges with just one step of electron-beam lithography. By optimizing a multilayer resist stack with a triple-exposure-dose scheme and a thermal reflow step, we achieve burr-free, suspended metallic bridges with sub-micron features that exhibit robust mechanical stability. Fabricated within a gradiometric SQUID design for superconducting transmon qubits, these airbridges introduce no measurable additional loss in the relaxation time T 1 , while enabling a 2.5-fold enhancement of the dephasing time T 2 * . This efficient method offers a practical route toward integrating high-performance three-dimensional interconnects in advanced quantum and nano-electronic devices.
In the upcoming decades quantum technologies, especially quantum computation, will have a strong influence on industrial, technological, economic, and social progress and are, therefore, considered to be one of the key technologies. The fundamental building blocks for quantum computation are quantum bits (qubits). The superconducting platform offers one of the most promising implementations due to its monolithic character and potential for scalability. Present research around the world primarily focusses on scaling up the number of qubits, so reliable wafer-scale fabrication technologies are mandatory. In this paper, we present our recent developments on wafer-scale fabrication of superconducting quantum circuits including Josephson junctions by the Manhattan-type technology. We discuss fabrication parameters as well as electrical characterization. For arrays out of 50 Josephson junctions with structure dimensions of 200 nm × 200 nm, we achieve a critical current standard deviation of approx. 3% on-chip and 7% on-wafer. We also show first measurement results of so fabricated transmon-type qubits with relaxation and decoherence times ofT1= 12.5 µs andT2= 15.0 µs, respectively. With an increasing number of superconducting qubits and, thus, their input and read-out lines, new challenges arise: Crosstalk between qubits, unwanted modes in the qubit environment, and required interconnections. One way to counteract is the implementation of low inductance connections across coplanar waveguides. This can be realized by aluminum air bridges. In this paper we discuss the air bridges’ fabrication parameters and the impact on the integrated circuits’ elements, e.g., Josephson junctions. We show electrical and superconducting measurements with critical temperatures and critical currents ofTc> 1.0 K andIc> 0.6 mA, respectively.