Nanofabrication techniques for superconducting qubits rely on resist-based masks patterned by electron-beam or optical lithography. We have developed an alternative nanofabrication technique based on free-standing silicon shadow masks fabricated from silicon-on-insulator wafers. These silicon shadow masks not only eliminate organic residues associated with resist-based lithography, but also provide a pathway to better understand and control surface-dielectric losses in superconducting qubits by decoupling mask fabrication from substrate preparation. We have successfully fabricated aluminum 3D transmon superconducting qubits with these shadow masks and found coherence quality factors comparable to those fabricated with standard techniques.
Nanofabrication techniques for superconducting qubits rely on resist-based masks patterned by electron-beam or optical lithography. We have developed an alternative nanofabrication technique based on free-standing silicon shadow masks fabricated from silicon-on-insulator wafers. These silicon shadow masks not only eliminate organic residues associated with resist-based lithography, but also provide a pathway to better understand and control surface-dielectric losses in superconducting qubits by decoupling mask fabrication from substrate preparation. We have successfully fabricated aluminum 3D transmon superconducting qubits with these shadow masks and found coherence quality factors comparable to those fabricated with standard techniques.
Improvements in circuit design and, more recently, in materials and surface cleaning have contributed to a rapid development of coherent superconducting qubits. However, organic resists commonly used for shadow evaporation of Josephson junctions (JJs) pose limitations due to residual contamination, poor thermal stability, and compatibility under typical surface-cleaning conditions. To provide an alternative, we developed an inorganic SiO2/Si3N4 on-chip stencil lithography mask for JJ fabrication. The stencil mask is resilient to aggressive cleaning agents and it withstands high temperatures up to 1200 °C, thereby opening new avenues for JJ material exploration and interface optimization. To validate the concept, we performed shadow evaporation of Al-based transmon qubits followed by stencil mask liftoff using vapor hydrofluoric acid, which selectively etches SiO2. We demonstrate an average T1≈75±11 μs over a 200 MHz frequency range across multiple cooldowns for one device, and T1≈44±8 μs for a second device. These results confirm the compatibility of stencil lithography with state-of-the-art superconducting quantum devices and motivate further investigations into materials engineering, film deposition, and surface cleaning techniques.
Abstract Surface dielectric loss remains a primary bottleneck limiting the energy relaxation time ( T 1 ) of super-conducting qubits. In particular, the amorphization damage introduced by in-situ argon ion milling on silicon (Si) substrates during junction fabrication constitutes a critical local loss channel. Addressing the vulnerability of the junction substrate in the conventional Manhattan process, we propose a bandage-free, shadow-masked angled ion milling technique that is fully compatible with existing mask layouts to enhance the coherence of Ta-on-Si transmons. This process leverages the geometric masking effect of a high-aspect-ratio bilayer resist, combined with a 45° azimuthal ion beam alignment, to isolate the sensitive cross-junction region from direct ion bombardment while ensuring reliable superconducting interconnections under gentle milling conditions. Cryogenic characterization across three independent cooldowns demonstrates that the 45° angled milling effectively enhances qubit performance, with the sample-average T 1 improving from 67.4 μs in the standard 0° process to 98.7 μs, and the average quality factor ( Q ) increasing from 2.0×10 6 to 2.5 × 10 6 . This work offers a practical nanofabrication strategy to suppress junction-region processing loss, providing a viable pathway for high-coherence silicon-based quantum processors.
Superconducting qubits stand as a pivotal platform for quantum computing, where scalable fabrication is crucial for building complex quantum circuits. Here, we develop a fabrication process for Nb/Al-AlOx/Nb tri-layer Josephson junctions on 4-inch silicon wafers using full-stepper lithography. Utilizing this process, we have produced both transmon and C-shunt flux qubits. The well-behavedI-Vcharacteristics of junction arrays containing up to 1000 junctions highlight the excellent uniformity and scalability of our process. Furthermore, by introducing a RIE pre-etch before BOE treatment to remove most of the SiO2insulator, we have suppressed dielectric loss and increased the coherence time of the Nb-based transmon qubit by almost 10 times, achieving a quality factor comparable to state-of-the-art Nb-based qubits on sapphire substrates. Given its compatibility with silicon technology, our method paves the way for the integration of multi-qubit processors and the co-fabrication of complex quantum circuits.
Superconducting qubit fabrication innovations continue to be explored to achieve higher performance. Despite improvements to base layer fabrication and processing, resist-based Josephson junction (JJ) schemes have largely remained unchanged. The polymer mask during deposition causes chemical contamination and limits in situ and ex situ surface preparation, junction materials, and scalability. Here, we demonstrate a resist-free approach to junction fabrication based on etched silicon trenches that is CMOS compatible and easily integrated into existing innovations in qubit base layer fabrication and chemical processing. We fabricate Al-AlOx-Al JJs and qubits using this method, measuring median energy relaxation times up to 184 microseconds. We find minimal contamination at the substrate-metal interface and fluctuations of energy relaxation on a 35 hour timescale that are narrow and normally distributed. The method widens the process window for substrate preparation and new materials platforms.
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T1 relaxation times averaging above 50 μs (Q>1.5×106). Current shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. This eliminates a key bottleneck in manufacturing superconducting qubits by reducing the fabrication time and cost. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty 0.5×0.5-cm2 chips, with junction areas ranging between 0.01 and 0.16 μm2. The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4% and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7%–2.5%. We show that 60%–70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.
Fabrication of sub-micron Josephson junctions is demonstrated using standard processing techniques for high-coherence, superconducting qubits. These junctions are made in two separate lithography steps with normal-angle evaporation. Most significantly, this work demonstrates that it is possible to achieve high coherence with junctions formed on aluminum surfaces cleaned in situ with Ar milling before the junction oxidation. This method eliminates the angle-dependent shadow masks typically used for small junctions. Therefore, this is conducive to the implementation of typical methods for improving margins and yield using conventional CMOS processing. The current method uses electron-beam lithography and an additive process to define the top and bottom electrodes. Extension of this work to optical lithography and subtractive processes is discussed.