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IEEE Transactions on Applied Superconductivity

Manufacturing of Superconducting Qubits Using Nb/Al-AlO x /Nb Josephson Junctions on Silicon Substrate

Qingjian Li, Y. F. Wu, Zhengqi Niu, Xiaoliang He, Wanpeng Gao, Wei Peng, Zheng Wang

Published Jan 28, 2026• 0 citations
Publisher

Abstract

Superconducting qubits stand as a pivotal platform for quantum computing, where scalable fabrication is crucial for building complex quantum circuits. Here, we develop a fabrication process for Nb/Al-AlOx/Nb tri-layer Josephson junctions on 4-inch silicon wafers using full-stepper lithography. Utilizing this process, we have produced both transmon and C-shunt flux qubits. The well-behavedI-Vcharacteristics of junction arrays containing up to 1000 junctions highlight the excellent uniformity and scalability of our process. Furthermore, by introducing a RIE pre-etch before BOE treatment to remove most of the SiO2insulator, we have suppressed dielectric loss and increased the coherence time of the Nb-based transmon qubit by almost 10 times, achieving a quality factor comparable to state-of-the-art Nb-based qubits on sapphire substrates. Given its compatibility with silicon technology, our method paves the way for the integration of multi-qubit processors and the co-fabrication of complex quantum circuits.

DOI
10.1109/tasc.2026.3657682

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Superconducting qubits stand as a pivotal platform for quantum computing, where scalable fabrication is crucial for building complex quantum circuits. Here, we develop a fabrication process for Nb/Al-AlOx/Nb tri-layer Josephson junctions on 4-inch silicon wafers using full-stepper lithography. Utilizing this process, we have produced both transmon and C-shunt flux qubits. The well-behavedI-Vcharacteristics of junction arrays containing up to 1000 junctions highlight the excellent uniformity and scalability of our process. Furthermore, by introducing a RIE pre-etch before BOE treatment to remove most of the SiO2insulator, we have suppressed dielectric loss and increased the coherence time of the Nb-based transmon qubit by almost 10 times, achieving a quality factor comparable to state-of-the-art Nb-based qubits on sapphire substrates. Given its compatibility with silicon technology, our method paves the way for the integration of multi-qubit processors and the co-fabrication of complex quantum circuits.
Superconducting qubits in today's quantum processing units are typically fabricated with angle-evaporated aluminum--aluminum-oxide--aluminum Josephson junctions. However, there is an urgent need to overcome the limited reproducibility of this approach when scaling up the number of qubits and junctions. Fabrication methods based on subtractive patterning of superconductor--insulator--superconductor trilayers, used for more classical large-scale Josephson junction circuits, could provide the solution but they in turn often suffer from lossy dielectrics incompatible with high qubit coherence. In this work, we utilize native aluminum oxide as a sidewall passivation layer for junctions based on aluminum--aluminum-oxide--niobium trilayers, and use such junctions in qubits. We design the fabrication process such that the few-nanometer-thin native oxide is not exposed to oxide removal steps that could increase its defect density or hinder its ability to prevent shorting between the leads of the junction. With these junctions, we design and fabricate transmon-like qubits and measure time-averaged coherence times up to 30 μμμs at a qubit frequency of 5 GHz, corresponding to a qubit quality factor of one million. Our process uses subtractive patterning and optical lithography on wafer scale, enabling high throughput in patterning. This approach provides a scalable path toward fabrication of superconducting qubits on industry-standard platforms.
Abstract Tantalum and aluminum on sapphire are widely used platforms for qubits of long coherent time. As quantum chips scale up, the number of Josephson junctions on Sapphire increases. Thus, both the uniformity and stability of the junctions are crucial to quantum devices, such as scalable superconducting quantum computer circuit, and quantum-limited amplifiers. By optimizing the fabrication process, especially, the conductive layer during the electron beam lithography process, Al/AlOx/Al junctions of sizes ranging from 0.0169 to 0.04 µm2 on sapphire substrates were prepared. The relative standard deviation of room temperature resistances (RN) of these junctions is better than 1.7% on 15 mm×15 mm chips, and better than 2.66% on 2 inch wafers, which is the highest uniformity on sapphire substrates has been reported. The junctions are robust and stable in resistances as temperature changes. The resistances increase by the ratio of 9.73% relative to RN as the temperature ramp down to 4K, and restore their initial values in the reverse process as the temperature ramps back to RT. After being stored in a nitrogen cabinet for 100 days, the resistance of the junctions changed by1.16% in average. The demonstration of uniform and stable Josephson junctions in large area paves the way for the fabrication of superconducting chip of hundreds of qubits on sapphire substrates.
We present the latest development of an Nb/Al-AlOx/Nb Josephson junction fabrication process for superconducting integrated circuits at SIMIT. Our fabrication process has four niobium superconducting layers and one Ti/Pd resistor layer with 1.0 Ω/square sheet resistor for junction shunting and circuit biasing. Critical current density Jcof the junctions is controlled from 30 A/cm2to 10 kA/cm2by exposing aluminum layer to pure or mixed O2atmosphere. Correlation between measured Jcand exposure conditions has been established. Average quality factor (Rsg/Rn) of the junctions in our process is larger than 20 with subgap leakage factor (Vm) beyond 30 mV. Critical current uniformity is obtained according to the switching current (Is) distribution of a 1000-JJ array. Measured standard deviation sigma of Isis less than 4% over the 100-mm wafer. Plasma resonance in a large Josephson junction is used to measure specific capacitance (Cs) of the junction. Sheet inductances of superconducting niobium strip-lines are extracted by a SQUID diagnose circuit and the measured results show good agreement with our design values.
Abstract The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers 1,2 . As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical 3 . Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal–oxide–semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 μs. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing 4 . Moreover, it offers the potential for further upscaling through three-dimensional integration 5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors.
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T1 relaxation times averaging above 50 μs (Q>1.5×106). Current shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. This eliminates a key bottleneck in manufacturing superconducting qubits by reducing the fabrication time and cost. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty 0.5×0.5-cm2 chips, with junction areas ranging between 0.01 and 0.16 μm2. The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4% and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7%–2.5%. We show that 60%–70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.
Abstract Josephson tunnel junctions form the basis for various superconductor electronic devices. For this reason, enormous efforts are routinely taken to establish and later on maintain a scalable and reproducible wafer-scale manufacturing process for high-quality Josephson junctions. Here, we present an anodization-free fabrication process for Nb/Al-AlO x /Nb cross-type Josephson junctions that requires only a small number of process steps and that is in general intrinsically compatible with wafer-scale fabrication. We show that the fabricated junctions are of very high quality and, compared to other junction types, exhibit not only a significantly reduced capacitance but also an almost rectangular critical current density profile. Our process hence enables the usage of low capacitance Josephson junctions for superconductor electronic devices such as ultra-low noise dc-superconducting quantum interference devices (SQUIDs), microwave SQUID multiplexers based on non-hysteretic rf-SQUIDs and RFSQ circuits.