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IEE Proceedings - Science Measurement and Technology

CMOS compatible fabrication methodsfor submicron Josephson junction qubits

A. Potts, G.J. Parker, J.J. Baumberg, P.A.J. de Groot

Published Sep 5, 2001• 38 citations
Publisher

Abstract

The authors have developed two distinct processes for the fabrication of mesoscopic Josephson junction qubits that are compatible with conventional CMOS processing. These devices, based on superconducting Al/Al2O3/Al tunnel junctions, are fabricated by electron beam lithography using single-layer and multi-layer resists. The new single-layer resist process is found to have significant advantages over conventional fabrication methods using suspended tri-layer shadow masks. It is simpler and more accurate to implement, and avoids the significant areas of redundant metallisation that are an unavoidable by-product of the tri-layer shadow mask method.

DOI
10.1049/ip-smt:20010395

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The authors have developed two distinct processes for the fabrication of mesoscopic Josephson junction qubits that are compatible with conventional CMOS processing. These devices, based on superconducting Al/Al2O3/Al tunnel junctions, are fabricated by electron beam lithography using single-layer and multi-layer resists. The new single-layer resist process is found to have significant advantages over conventional fabrication methods using suspended tri-layer shadow masks. It is simpler and more accurate to implement, and avoids the significant areas of redundant metallisation that are an unavoidable by-product of the tri-layer shadow mask method.
Fabrication of sub-micron Josephson junctions is demonstrated using standard processing techniques for high-coherence, superconducting qubits. These junctions are made in two separate lithography steps with normal-angle evaporation. Most significantly, this work demonstrates that it is possible to achieve high coherence with junctions formed on aluminum surfaces cleaned in situ with Ar milling before the junction oxidation. This method eliminates the angle-dependent shadow masks typically used for small junctions. Therefore, this is conducive to the implementation of typical methods for improving margins and yield using conventional CMOS processing. The current method uses electron-beam lithography and an additive process to define the top and bottom electrodes. Extension of this work to optical lithography and subtractive processes is discussed.
Superconducting qubit fabrication innovations continue to be explored to achieve higher performance. Despite improvements to base layer fabrication and processing, resist-based Josephson junction (JJ) schemes have largely remained unchanged. The polymer mask during deposition causes chemical contamination and limits in situ and ex situ surface preparation, junction materials, and scalability. Here, we demonstrate a resist-free approach to junction fabrication based on etched silicon trenches that is CMOS compatible and easily integrated into existing innovations in qubit base layer fabrication and chemical processing. We fabricate Al-AlOx-Al JJs and qubits using this method, measuring median energy relaxation times up to 184 microseconds. We find minimal contamination at the substrate-metal interface and fluctuations of energy relaxation on a 35 hour timescale that are narrow and normally distributed. The method widens the process window for substrate preparation and new materials platforms.
The superconductive Josephson junction is the key device for superconducting quantum computation. We have fabricated Al/Al2O3/Al tunnel junctions using a double angle evaporation method based on a suspended shadow mask. The Al2O3 junction barrier has been formed by introducing pure oxygen into the chamber during the fabrication process. We have adjusted exposure conditions by changing either the oxygen pressure or the oxidizing time during the formation of tunnel barriers to control the critical current density J c and the junction specific resistance R c . Measurements of the leakage in Al/Al2O3/Al tunnel junctions show that the devices are suitable for qubit applications.
Josephson tunnel junctions are the centerpiece of almost any superconducting electronic circuit, including qubits. Typically, the junctions for qubits are fabricated using shadow evaporation techniques to reduce dielectric loss contributions from the superconducting film interfaces. In recent years, however, sub-micrometer scale overlap junctions have started to attract attention. Compared to shadow mask techniques, neither an angle dependent deposition nor free-standing bridges or overlaps are needed, which are significant limitations for wafer-scale processing. This comes at the cost of breaking the vacuum during fabrication, but simplifies integration in multi-layered circuits and implementation of vastly different junction sizes and enables fabrication on a larger scale in an industrially standardized process. In this work, we demonstrate the feasibility of a subtractive process for the fabrication of overlap junctions. In an array of test contacts, we find low aging of the average normal state resistance of only 1.6% over 6 months. We evaluate the coherence properties of the junctions by employing them in superconducting transmon qubits. In time domain experiments, we find that both, the qubit life- and coherence time of our best device, are, on average, greater than 20 μs. Finally, we discuss potential improvements to our technique. This work paves the way toward a more standardized process flow with advanced materials and growth processes, and constitutes an important step for the large scale fabrication of superconducting quantum circuits.
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T1 relaxation times averaging above 50 μs (Q>1.5×106). Current shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. This eliminates a key bottleneck in manufacturing superconducting qubits by reducing the fabrication time and cost. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty 0.5×0.5-cm2 chips, with junction areas ranging between 0.01 and 0.16 μm2. The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4% and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7%–2.5%. We show that 60%–70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.
We have developed a combined photolithography and electron-beam lithography fabrication process for sub-\mum to \mum-size Nb/Al-AlOx/Nb Josephson junctions. In order to define the junction size and protect its top electrode during anodic oxidation, we developed and used the new concept of an aluminum hard mask. Josephson junctions of sizes down to 0.5 \mum2 have been fabricated and thoroughly characterized. We found that they have a very high quality, which is witnessed by the IV curves with quality parameters Vm > 50 mV and Vgap = 2.8 mV at 4.2 K, as well as IcRN products of 1.75-1.93 mV obtained at lower temperatures. In order to test the usability of our fabrication process for superconducting quantum bits, we have also designed, fabricated and experimentally investigated phase qubits made of these junctions. We found a relaxation time of T1 = 26 ns and a dephasing time of T2 = 21 ns.