Improvement of Josephson junction uniformity via early‐stage junction formation for scalable qubit production
Hyoungkug Kim, Kiho Kim, Jeongmin Shim, Sunje Kim, Insu Jeon, Daeseok Han, Hyeokshin Kwon, ChungSun Lee, Geunyong Kim, Eun-A Kim, Dongmin Kim, Jaeho Shin, Daeyun Kim
Abstract To maximize the yield of scalable superconducting quantum processors, we introduce a fabrication strategy that prioritizes the formation of Josephson junctions (JJs) before the shunting capacitors. The junction-first approach minimizes the impact of accumulated process-induced surface modifications on the JJ interface. We show through wafer-scale statistical measurements that this sequence substantially reduces fluctuations in junction resistance across different wafers. Surface analysis via transmission electron microscopy and atomic force microscopy identifies that preceding lithography and etching steps in conventional workflows damage the substrate surface, leading to non-uniform junction morphology. The compatibility of this process with high-performance qubit operation is demonstrated through the fabrication of an eight-qubit quantum processing unit. The resulting coherence times remain sufficient for fully functional qubit operation, confirming that that the junction-first process significantly enhances junction reproducibility while maintaining viable qubit performance, offering a scalable pathway for next-generation quantum hardware.
Abstract To maximize the yield of scalable superconducting quantum processors, we introduce a fabrication strategy that prioritizes the formation of Josephson junctions (JJs) before the shunting capacitors. The junction-first approach minimizes the impact of accumulated process-induced surface modifications on the JJ interface. We show through wafer-scale statistical measurements that this sequence substantially reduces fluctuations in junction resistance across different wafers. Surface analysis via transmission electron microscopy and atomic force microscopy identifies that preceding lithography and etching steps in conventional workflows damage the substrate surface, leading to non-uniform junction morphology. The compatibility of this process with high-performance qubit operation is demonstrated through the fabrication of an eight-qubit quantum processing unit. The resulting coherence times remain sufficient for fully functional qubit operation, confirming that that the junction-first process significantly enhances junction reproducibility while maintaining viable qubit performance, offering a scalable pathway for next-generation quantum hardware.
Reproducible Josephson junction (JJ) characteristics are essential for frequency-deterministic and scalable superconducting quantum processors. We show that the normal-state resistance and its reproducibility in Al/AlOx/Al JJs are governed not by oxide thickness, but by fabrication-history–induced disorder in the tunneling barrier. By comparing junctions fabricated on bare wafers, lift-off–processed base layers, and dry-etched base layers under identical oxidation conditions, we observe large differences in resistance and wafer-to-wafer variability. Atomic force microscopy reveals distinct surface disorder imprinted by prior fabrication steps, while cross-sectional transmission electron microscopy show that the average AlOx barrier thickness is comparable across the three fabrication histories within experimental uncertainty. The enhanced resistance on rough, plasma-damaged surfaces therefore originates from nanoscale barrier disorder rather than thickness variations. These results establish fabrication history as a key determinant of JJ barrier quality and highlight the need for holistic process control to achieve deterministic qubit frequency targeting.
Superconducting qubits stand as a pivotal platform for quantum computing, where scalable fabrication is crucial for building complex quantum circuits. Here, we develop a fabrication process for Nb/Al-AlOx/Nb tri-layer Josephson junctions on 4-inch silicon wafers using full-stepper lithography. Utilizing this process, we have produced both transmon and C-shunt flux qubits. The well-behavedI-Vcharacteristics of junction arrays containing up to 1000 junctions highlight the excellent uniformity and scalability of our process. Furthermore, by introducing a RIE pre-etch before BOE treatment to remove most of the SiO2insulator, we have suppressed dielectric loss and increased the coherence time of the Nb-based transmon qubit by almost 10 times, achieving a quality factor comparable to state-of-the-art Nb-based qubits on sapphire substrates. Given its compatibility with silicon technology, our method paves the way for the integration of multi-qubit processors and the co-fabrication of complex quantum circuits.
Fluxonium qubits are recognized for their high coherence times and high operation fidelities. These are attributed to their unique design incorporating a superinductor, which is typically implemented using an array of over 100 Josephson junctions; however, this complexity poses significant fabrication challenges, particularly in achieving high yield and junction uniformity with traditional methods. Here, we introduce an overlap process for Josephson-junction fabrication that achieves nearly 100% yield and maintains uniformity across a 2-inch (50.8-mm) wafer with less than 5% variation for the phase-slip junction and less than 2% for the entire junction array. We use a compact junction array design that achieves state-of-the-art dielectric loss tangents and flux noise levels, as confirmed by multiple devices. This enables fluxonium qubits to reach energy relaxation times exceeding 1 ms at the flux-frustration point. This work paves the way for scalable, high-coherence fluxonium processors using processes compatible with complementary metal-oxide semiconductor manufacturing, marking a significant step toward practical quantum computing.
Quantum computing aims to leverage the principles of quantum mechanics to achieve superior information processing capabilities beyond the limits of today's computers. These machines have the potential to efficiently simulate quantum mechanical systems, revolutionizing the development of new materials, drug discovery, and fundamental physics research. Additionally, algorithms such as prime factorization and unstructured data search offer significant speed-ups on quantum computers, enhancing computational capabilities beyond current limits. The first experimental demonstrations of this central idea have sparked significant excitement and expectation in society. Superconducting circuit hardware technologies, which implement quantum computers, are rapidly maturing and transitioning from physics laboratories to industrial fabrication plants. This work aims to bridge the gap between physics laboratory fabrication techniques and industrial standards. Here, the approach starts from complementary metal-oxide-semiconductor (CMOS) compatible processes, optimized using insights from the decades of laboratory development. In particular, two alternative Josephson junction (JJ) fabrication methods are explored, the overlap junction and tri-layer junction approaches, that do not rely on the standard angled evaporation and lift-off processes. These CMOS-compatible fabrication processes are benchmarked for quality and uniformity, using superconducting resonators and qubits to probe material defects and process variability. Device metrics are used to identify and optimize the most critical fabrication steps. Using these methods, a successful overlap JJ qubit fabrication flow is demonstrated with industry standard tools on 300 mm wafer scale, achieving an initial qubit yield of 98.25%. Several devices exhibit lifetimes and coherence times exceeding 100 microseconds, comparable to state-of-the-art devices. Extensive across-wafer measurements and analysis provide insights into limiting factors such as material defects at device interfaces, identifying avenues for continued improvements. The second method, the tri-layer JJ approach, has the potential for defect-free devices with CMOS-grade uniformity by growing epitaxial junctions, patterned with advanced lithography and dry-etch techniques. However, subsequent metallization steps introduce detrimental microwave losses compromising the pristine junctions. Here, a novel tri-layer qubit design is proposed, the tri-layer merged element transmon (tri-MET), which eliminates further processing beyond pristine junction deposition and patterning. The new device is demonstrated in simulation, and initial fabrication steps are presented. In summary, this thesis presents key breakthroughs in superconducting qubit fabrication methods, providing evidence for the viability of industrial methods to fabricate high-coherence superconducting qubits. Further work will focus on addressing interface defects, improving junction uniformity, and incorporating three-dimensional integration techniques to enable large-scale quantum processors for computations beyond the classical limits.
Abstract Quantum bits, or qubits, are an example of coherent circuits envisioned for next-generation computers and detectors. A robust superconducting qubit with a coherent lifetime of O(100 µs) is the transmon: a Josephson junction functioning as a non-linear inductor shunted with a capacitor to form an anharmonic oscillator. In a complex device with many such transmons, precise control over each qubit frequency is often required, and thus variations of the junction area and tunnel barrier thickness must be sufficiently minimized to achieve optimal performance while avoiding spectral overlap between neighboring circuits. Simply transplanting our recipe optimized for single, stand-alone devices to wafer-scale (producing 64, 1x1 cm dies from a 150 mm wafer) initially resulted in global drifts in room-temperature tunneling resistance of ± 30%. Inferring a critical current I c variation from this resistance distribution, we present an optimized process developed from a systematic 38 wafer study that results in < 3.5% relative standard deviation (RSD) in critical current ( ≡ σ I c / I c ) for 3000 Josephson junctions (both single-junctions and asymmetric SQUIDs) across an area of 49 cm2. Looking within a 1x1 cm moving window across the substrate gives an estimate of the variation characteristic of a given qubit chip. Our best process, utilizing ultrasonically assisted development, uniform ashing, and dynamic oxidation has shown σ I c / I c = 1.8% within 1x1 cm, on average, with a few 1x1 cm areas having σ I c / I c < 1.0% (equivalent to σ f / f < 0.5%). Such stability would drastically improve the yield of multi-junction chips with strict critical current requirements.
Superconducting qubit fabrication innovations continue to be explored to achieve higher performance. Despite improvements to base layer fabrication and processing, resist-based Josephson junction (JJ) schemes have largely remained unchanged. The polymer mask during deposition causes chemical contamination and limits in situ and ex situ surface preparation, junction materials, and scalability. Here, we demonstrate a resist-free approach to junction fabrication based on etched silicon trenches that is CMOS compatible and easily integrated into existing innovations in qubit base layer fabrication and chemical processing. We fabricate Al-AlOx-Al JJs and qubits using this method, measuring median energy relaxation times up to 184 microseconds. We find minimal contamination at the substrate-metal interface and fluctuations of energy relaxation on a 35 hour timescale that are narrow and normally distributed. The method widens the process window for substrate preparation and new materials platforms.