Fluxonium qubits are recognized for their high coherence times and high operation fidelities. These are attributed to their unique design incorporating a superinductor, which is typically implemented using an array of over 100 Josephson junctions; however, this complexity poses significant fabrication challenges, particularly in achieving high yield and junction uniformity with traditional methods. Here, we introduce an overlap process for Josephson-junction fabrication that achieves nearly 100% yield and maintains uniformity across a 2-inch (50.8-mm) wafer with less than 5% variation for the phase-slip junction and less than 2% for the entire junction array. We use a compact junction array design that achieves state-of-the-art dielectric loss tangents and flux noise levels, as confirmed by multiple devices. This enables fluxonium qubits to reach energy relaxation times exceeding 1 ms at the flux-frustration point. This work paves the way for scalable, high-coherence fluxonium processors using processes compatible with complementary metal-oxide semiconductor manufacturing, marking a significant step toward practical quantum computing.
Fluxonium qubits are recognized for their high coherence times and high operation fidelities. These are attributed to their unique design incorporating a superinductor, which is typically implemented using an array of over 100 Josephson junctions; however, this complexity poses significant fabrication challenges, particularly in achieving high yield and junction uniformity with traditional methods. Here, we introduce an overlap process for Josephson-junction fabrication that achieves nearly 100% yield and maintains uniformity across a 2-inch (50.8-mm) wafer with less than 5% variation for the phase-slip junction and less than 2% for the entire junction array. We use a compact junction array design that achieves state-of-the-art dielectric loss tangents and flux noise levels, as confirmed by multiple devices. This enables fluxonium qubits to reach energy relaxation times exceeding 1 ms at the flux-frustration point. This work paves the way for scalable, high-coherence fluxonium processors using processes compatible with complementary metal-oxide semiconductor manufacturing, marking a significant step toward practical quantum computing.
We report superconducting fluxonium qubits with coherence times largely limited by energy relaxation and reproducibly satisfying T 2 > 100 μs (T 2 > 400 μs in one device).Moreover, given the state-of-the-art values of the surface loss tangent and the 1=f flux-noise amplitude, the coherence time can be further improved beyond 1 ms.Our results violate a common viewpoint that the number of Josephson junctions in a superconducting circuit-over 10 2 here-must be minimized for best qubit coherence.We outline how the unique to fluxonium combination of long coherence time and large anharmonicity can benefit both gate-based and adiabatic quantum computing.
Abstract The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers 1,2 . As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical 3 . Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal–oxide–semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 μs. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing 4 . Moreover, it offers the potential for further upscaling through three-dimensional integration 5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors.
Superconducting qubits stand as a pivotal platform for quantum computing, where scalable fabrication is crucial for building complex quantum circuits. Here, we develop a fabrication process for Nb/Al-AlOx/Nb tri-layer Josephson junctions on 4-inch silicon wafers using full-stepper lithography. Utilizing this process, we have produced both transmon and C-shunt flux qubits. The well-behavedI-Vcharacteristics of junction arrays containing up to 1000 junctions highlight the excellent uniformity and scalability of our process. Furthermore, by introducing a RIE pre-etch before BOE treatment to remove most of the SiO2insulator, we have suppressed dielectric loss and increased the coherence time of the Nb-based transmon qubit by almost 10 times, achieving a quality factor comparable to state-of-the-art Nb-based qubits on sapphire substrates. Given its compatibility with silicon technology, our method paves the way for the integration of multi-qubit processors and the co-fabrication of complex quantum circuits.
Fluxonium superconducting qubits have demonstrated long coherence times and high single- and two-qubit gate fidelities, making them a favorable building block for superconducting quantum processors. We investigate the dominant limitations to fluxonium qubit energy relaxation time T1 using a set of eight planar, aluminum-on-silicon qubits. We find that a circuit-based model for capacitive dielectric loss best captures the frequency dependence of T1, which we analyze within both a two-level and a six-level energy relaxation model. We convert the measured T1 into an effective capacitive quality factor QCeff to compare qubits on equal footing, accounting for independently estimated contributions from 1/f flux noise and radiative loss to the control and readout circuitry. We apply this methodology to compare qubits from two fabrication processes: a baseline process and one that applies a fluorine-based wet treatment prior to Josephson junction deposition. We resolve a small improvement of (13.8 ± 8.4)% in the process mean QCeff, indicating that the fluorine treatment may have reduced loss from the metal-substrate interface, but did not address the primary source of loss in these fluxonium qubits.
Quantum computing aims to leverage the principles of quantum mechanics to achieve superior information processing capabilities beyond the limits of today's computers. These machines have the potential to efficiently simulate quantum mechanical systems, revolutionizing the development of new materials, drug discovery, and fundamental physics research. Additionally, algorithms such as prime factorization and unstructured data search offer significant speed-ups on quantum computers, enhancing computational capabilities beyond current limits. The first experimental demonstrations of this central idea have sparked significant excitement and expectation in society. Superconducting circuit hardware technologies, which implement quantum computers, are rapidly maturing and transitioning from physics laboratories to industrial fabrication plants. This work aims to bridge the gap between physics laboratory fabrication techniques and industrial standards. Here, the approach starts from complementary metal-oxide-semiconductor (CMOS) compatible processes, optimized using insights from the decades of laboratory development. In particular, two alternative Josephson junction (JJ) fabrication methods are explored, the overlap junction and tri-layer junction approaches, that do not rely on the standard angled evaporation and lift-off processes. These CMOS-compatible fabrication processes are benchmarked for quality and uniformity, using superconducting resonators and qubits to probe material defects and process variability. Device metrics are used to identify and optimize the most critical fabrication steps. Using these methods, a successful overlap JJ qubit fabrication flow is demonstrated with industry standard tools on 300 mm wafer scale, achieving an initial qubit yield of 98.25%. Several devices exhibit lifetimes and coherence times exceeding 100 microseconds, comparable to state-of-the-art devices. Extensive across-wafer measurements and analysis provide insights into limiting factors such as material defects at device interfaces, identifying avenues for continued improvements. The second method, the tri-layer JJ approach, has the potential for defect-free devices with CMOS-grade uniformity by growing epitaxial junctions, patterned with advanced lithography and dry-etch techniques. However, subsequent metallization steps introduce detrimental microwave losses compromising the pristine junctions. Here, a novel tri-layer qubit design is proposed, the tri-layer merged element transmon (tri-MET), which eliminates further processing beyond pristine junction deposition and patterning. The new device is demonstrated in simulation, and initial fabrication steps are presented. In summary, this thesis presents key breakthroughs in superconducting qubit fabrication methods, providing evidence for the viability of industrial methods to fabricate high-coherence superconducting qubits. Further work will focus on addressing interface defects, improving junction uniformity, and incorporating three-dimensional integration techniques to enable large-scale quantum processors for computations beyond the classical limits.
Abstract As the superconducting qubit platform matures towards ever-larger scales in the race towards a practical quantum computer, limitations due to qubit inhomogeneity through lack of process control become apparent. To benefit from the advanced process control in industry-scale CMOS fabrication facilities, different processing methods will be required. In particular, the double-angle evaporation and lift-off techniques used for current, state-of-the-art superconducting qubits are generally incompatible with modern-day manufacturable processes. Here, we demonstrate a fully CMOS compatible qubit fabrication method, and show results from overlap Josephson junction devices with long coherence and relaxation times, on par with the state-of-the-art. We experimentally verify that Argon milling—the critical step during junction fabrication—and a subtractive-etch process nevertheless result in qubits with average qubit energy relaxation times T 1 reaching 70 µs, with maximum values exceeding 100 µs. Furthermore, we show that our results are still limited by surface losses and not, crucially, by junction losses. The presented fabrication process, therefore, heralds an important milestone towards a manufacturable 300 mm CMOS process for high-coherence superconducting qubits and has the potential to advance the scaling of superconducting device architectures.