We develop a fully complementary metal-oxide semiconductor (CMOS) fabrication technique for the realization of a superconducting qubit network (SQN). In our current research work, we focus on a single-angle overlap Josephson junction fabrication technique, based on the lift-off process for defining both base and top electrodes, avoiding the wiring insulator layer and requiring an RF Ar etching process before AlOxbarrier growth. The fabricated Al/AlOx/Al microscale Josephson junctions have been tested at low temperature (T = 300 mK) in the superconducting state using current–voltage characteristic measurements.
We develop a fully complementary metal-oxide semiconductor (CMOS) fabrication technique for the realization of a superconducting qubit network (SQN). In our current research work, we focus on a single-angle overlap Josephson junction fabrication technique, based on the lift-off process for defining both base and top electrodes, avoiding the wiring insulator layer and requiring an RF Ar etching process before AlOxbarrier growth. The fabricated Al/AlOx/Al microscale Josephson junctions have been tested at low temperature (T = 300 mK) in the superconducting state using current–voltage characteristic measurements.
Fabrication of sub-micron Josephson junctions is demonstrated using standard processing techniques for high-coherence, superconducting qubits. These junctions are made in two separate lithography steps with normal-angle evaporation. Most significantly, this work demonstrates that it is possible to achieve high coherence with junctions formed on aluminum surfaces cleaned in situ with Ar milling before the junction oxidation. This method eliminates the angle-dependent shadow masks typically used for small junctions. Therefore, this is conducive to the implementation of typical methods for improving margins and yield using conventional CMOS processing. The current method uses electron-beam lithography and an additive process to define the top and bottom electrodes. Extension of this work to optical lithography and subtractive processes is discussed.
Abstract As the superconducting qubit platform matures towards ever-larger scales in the race towards a practical quantum computer, limitations due to qubit inhomogeneity through lack of process control become apparent. To benefit from the advanced process control in industry-scale CMOS fabrication facilities, different processing methods will be required. In particular, the double-angle evaporation and lift-off techniques used for current, state-of-the-art superconducting qubits are generally incompatible with modern-day manufacturable processes. Here, we demonstrate a fully CMOS compatible qubit fabrication method, and show results from overlap Josephson junction devices with long coherence and relaxation times, on par with the state-of-the-art. We experimentally verify that Argon milling—the critical step during junction fabrication—and a subtractive-etch process nevertheless result in qubits with average qubit energy relaxation times T 1 reaching 70 µs, with maximum values exceeding 100 µs. Furthermore, we show that our results are still limited by surface losses and not, crucially, by junction losses. The presented fabrication process, therefore, heralds an important milestone towards a manufacturable 300 mm CMOS process for high-coherence superconducting qubits and has the potential to advance the scaling of superconducting device architectures.
The performance of superconducting electronic devices such as superconducting quantum bits (qubits) and superconducting quantum interference devices (SQUIDs) strongly relies on high-quality Josephson junctions (JJ) and their integration into surrounding circuit elements. Therefore, a corresponding fabrication technology should allow for the fabrication of all required elements including the JJs, inductances, capacitances and waveguides. For a long time, shadow evaporation technique was the state of the art for the implementation of sub-μ m sized JJs based on aluminum for qubits of high coherence times. Although, the use of a single lithographic step represents a major advantage of this technique. However, shadowing effects limit sample size, device complexity, and thus scalability of the circuitry. To overcome these limitations and to meet the demands of next generation scalable quantum circuits, in this work we introduce our cross -type JJ aluminum technology, where JJs are defined by the overlap of two narrow perpendicular stripes. We discuss the technological challenges, with a focus on our newly developed dry etching process for patterning of the aluminum thin film. Compared to a lift-off based process, this advanced wafer-scale fabrication technology offers a high integration density and the required design flexibility. We will present first results on cross -type aluminum JJs.
We present a fabrication scheme and testing results for epitaxial sub-micrometer Josephson junctions. The junctions are made using a high-temperature (1170 K) "via process" yielding junctions as small as 0.8 mu m in diameter by use of optical lithography. Sapphire (Al2O3) tunnel-barriers are grown on an epitaxial Re/Ti multilayer base-electrode. We have fabricated devices with both Re and Al top electrodes. While room-temperature (295 K) resistance versus area data are favorable for both types of top electrodes, the low-temperature (50 mK) data show that junctions with the Al top electrode have a much higher subgap resistance. The microwave loss properties of the junctions have been measured by use of superconducting Josephson junction qubits. The results show that high subgap resistance correlates to improved qubit performance.
Superconducting qubit fabrication innovations continue to be explored to achieve higher performance. Despite improvements to base layer fabrication and processing, resist-based Josephson junction (JJ) schemes have largely remained unchanged. The polymer mask during deposition causes chemical contamination and limits in situ and ex situ surface preparation, junction materials, and scalability. Here, we demonstrate a resist-free approach to junction fabrication based on etched silicon trenches that is CMOS compatible and easily integrated into existing innovations in qubit base layer fabrication and chemical processing. We fabricate Al-AlOx-Al JJs and qubits using this method, measuring median energy relaxation times up to 184 microseconds. We find minimal contamination at the substrate-metal interface and fluctuations of energy relaxation on a 35 hour timescale that are narrow and normally distributed. The method widens the process window for substrate preparation and new materials platforms.
Researches on the fabrication of ~ 0.1 × 0.1 μ m 2 superconductor–insulator–superconductor (SIS) Josephson junctions are reviewed. Today, a typical dimension is 1–10 μm for Josephson junctions in superconducting integrated circuits. These Josephson junctions are defined by well-established photolithographic technology with reactive ion etching (RIE), and for the superconductor, Nb is almost always used. The merits of Nb include the facts that the superconducting transition temperature Tc of Nb (9.2 K ) is higher than the boiling point of He (4.2 K ), and that Nb has excellent stability against thermal cycling between room temperature and liquid- He temperature. For the fabrication of ~ 0.1 × 0.1 μ m 2 junctions, on the other hand, there is a standard process with electron-beam lithography, shadow evaporation, and lift-off. This process works well for Al (Tc = 1.2 K ), however, it is not ideal for Nb . The scope of this brief review is the nanoscale junction with Nb electrodes. We will look at the efforts of optimizing the standard lift-off process for Nb , electron-beam-lithographic versions of the Nb Josephson-junction technology, focused-ion-beam (FIB) etching as a convenient alternative to electron-beam lithography and RIE, etc. In order to characterize nanoscale tunnel junctions, the single-charge transistor has been often fabricated. Therefore, a summary of its theoretical transport properties is also included.