arXiv:1108.1830 · Superconductor Science and Technology
Sub-micrometer epitaxial Josephson junctions for quantum circuits
Jeffrey S Kline, Michael R. Vissers, Fabio C S da Silva, David S Wisbey, Martin P. Weides, Terence J. Weir, Benjamin Turek, Danielle Braje, William D. Oliver, Yoni Shalibo, Nadav Katz, Blake R Johnson, Thomas A Ohki, David P Pappas
We present a fabrication scheme and testing results for epitaxial sub-micrometer Josephson junctions. The junctions are made using a high-temperature (1170 K) "via process" yielding junctions as small as 0.8 mu m in diameter by use of optical lithography. Sapphire (Al2O3) tunnel-barriers are grown on an epitaxial Re/Ti multilayer base-electrode. We have fabricated devices with both Re and Al top electrodes. While room-temperature (295 K) resistance versus area data are favorable for both types of top electrodes, the low-temperature (50 mK) data show that junctions with the Al top electrode have a much higher subgap resistance. The microwave loss properties of the junctions have been measured by use of superconducting Josephson junction qubits. The results show that high subgap resistance correlates to improved qubit performance.
We present a fabrication scheme and testing results for epitaxial sub-micrometer Josephson junctions. The junctions are made using a high-temperature (1170 K) "via process" yielding junctions as small as 0.8 mu m in diameter by use of optical lithography. Sapphire (Al2O3) tunnel-barriers are grown on an epitaxial Re/Ti multilayer base-electrode. We have fabricated devices with both Re and Al top electrodes. While room-temperature (295 K) resistance versus area data are favorable for both types of top electrodes, the low-temperature (50 mK) data show that junctions with the Al top electrode have a much higher subgap resistance. The microwave loss properties of the junctions have been measured by use of superconducting Josephson junction qubits. The results show that high subgap resistance correlates to improved qubit performance.
Josephson tunnel junctions represent a key element in superconducting electronics and quantum circuits. For many years, shadow evaporation by means of Dolan-type bridges has been the state-of-the-art for deep sub- micrometer sized structures. Increasing demand in the number of Josephson junctions, e.g. in qubit circuits and travelling wave parametric amplifiers, requests for a wafer-scale fabrication process with precise control of junction parameters and have led to an advanced lift-off technique called Manhattan-type junction technology in recent years. Herein, we report on the development of a 100 mm wafer-scale fabrication technology for deep sub-micrometer sized Al Josephson junctions with linear dimensions down to 180 nm. The critical currentICof the junctions ranges from about 10 to 120 nA scaling with their linear dimensions. Low temperature transport measurements as well as room-temperature characterization has been used forICand process homogeneity determination of series arrays of up to 50 Josephson junctions. We discuss technology parameters such as yield, on-chip and on-wafer reproducibility of the junction's critical currents as well as main process limitations. Moreover, we present experimental results on the characterization of first transmon-type qubits fabricated using this technology.
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T1 relaxation times averaging above 50 μs (Q>1.5×106). Current shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. This eliminates a key bottleneck in manufacturing superconducting qubits by reducing the fabrication time and cost. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty 0.5×0.5-cm2 chips, with junction areas ranging between 0.01 and 0.16 μm2. The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4% and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7%–2.5%. We show that 60%–70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.
Fabrication of sub-micron Josephson junctions is demonstrated using standard processing techniques for high-coherence, superconducting qubits. These junctions are made in two separate lithography steps with normal-angle evaporation. Most significantly, this work demonstrates that it is possible to achieve high coherence with junctions formed on aluminum surfaces cleaned in situ with Ar milling before the junction oxidation. This method eliminates the angle-dependent shadow masks typically used for small junctions. Therefore, this is conducive to the implementation of typical methods for improving margins and yield using conventional CMOS processing. The current method uses electron-beam lithography and an additive process to define the top and bottom electrodes. Extension of this work to optical lithography and subtractive processes is discussed.
Sub-μm Josephson Junctions for Superconducting Quantum Devices
For high-performance superconducting quantum devices based on Josephson junctions (JJs), decreasing lateral sizes is of great importance. Fabrication of sub-μm JJs is challenging, due to nonflat surfaces with step heights of up to several 100 nm generated during the fabrication process. We have refined a fabrication process with significantly decreased film thicknesses, resulting in almost flat surfaces at intermediate steps during the JJ definition. In combination with a mix-and-match process, combining electron-beam lithography and conventional photolithography, we can fabricate JJs with lateral dimensions down to 0.023 μm2. We propose this refined process as an alternative to the commonly used chemical-mechanical polishing procedure. Transport measurements of JJs, having critical-current densities ranging from 50 to 104A/cm2, are presented at 4.2 K. Our JJ process yields excellent quality parameters, Rsg/RNup to ~ 50, Vmfrom 15 to 80 mV and Vgapup to 2.81 mV, and also allows the fabrication of high-quality, sub-μm wide, long JJs (LJJs) for the study of Josephson vortex behavior. The developed technique can also be used for similar multilayer processes and is very promising for fabricating sub- μm JJs for quantum devices such as SQUIDs, qubits, and SIS mixers.
The Josephson junction is a crucial element in superconducting devices, and niobium is a promising candidate for the superconducting material due to its large energy gap relative to aluminum. AlOx has long been regarded as the highest quality oxide tunnel barrier and is often used in niobium-based junctions. Here, we propose ZrOx as an alternative tunnel barrier material for Nb electrodes. We theoretically estimate that zirconium oxide has excellent oxygen retention properties and experimentally verify that there is no significant oxygen diffusion leading to NbOx formation in the adjacent Nb electrode. We develop a top–down, subtractive fabrication process for Nb/Zr–ZrOx/Nb Josephson junctions, which enables scalability and large-scale production of superconducting electronics. Using cross-sectional scanning transmission electron microscopy, we experimentally find that depending on the Zr thickness, ZrOx tunnel barriers can be fully crystalline with chemically abrupt interfaces with niobium. Further analysis using electron energy loss spectroscopy reveals that ZrOx corresponds to tetragonal ZrO2. Room temperature characterization of fabricated junctions using Simmons’ model shows that ZrO2 exhibits a low tunnel barrier height, which is promising in merged-element transmon applications. Low temperature transport measurements reveal sub-gap structure, while the low-voltage sub-gap resistance remains in the megaohm range.
We develop a fully complementary metal-oxide semiconductor (CMOS) fabrication technique for the realization of a superconducting qubit network (SQN). In our current research work, we focus on a single-angle overlap Josephson junction fabrication technique, based on the lift-off process for defining both base and top electrodes, avoiding the wiring insulator layer and requiring an RF Ar etching process before AlOxbarrier growth. The fabricated Al/AlOx/Al microscale Josephson junctions have been tested at low temperature (T = 300 mK) in the superconducting state using current–voltage characteristic measurements.