We have undertaken the development of a chip-scale atomic clock (CSAC) whose design goals include short-term stability, sigma(sub y)(tau=1 hour), of 1x10(exp 11) with a total power consumption of 30 mW and an overall device volume of 1 cu cm. The stringent power requirement dominates the physics package architecture, dictating a small (<5 mm(exp 3) gaseous atomic ensemble interrogated by a low-power semiconductor laser. At PTTI 2002, we reported on initial experimental investigations leading to the decision to employ the coherent population trapping (CPT) interrogation technique. This paper describes our further progress on the CSAC effort, including the development of custom vertical cavity surface emitting laser (VCSEL) sources and techniques for microfabricating miniature cesium vapor cells comprised of anodically bonded silicon and glass. Measurements of the signal contrast and linewidth of both the cesium D1 and D2 resonance transitions are compared, and frequency stability measurements of the CSAC testbed are presented.
We have undertaken the development of a chip-scale atomic clock (CSAC) whose design goals include short-term stability, sigma(sub y)(tau=1 hour), of 1x10(exp 11) with a total power consumption of 30 mW and an overall device volume of 1 cu cm. The stringent power requirement dominates the physics package architecture, dictating a small (<5 mm(exp 3) gaseous atomic ensemble interrogated by a low-power semiconductor laser. At PTTI 2002, we reported on initial experimental investigations leading to the decision to employ the coherent population trapping (CPT) interrogation technique. This paper describes our further progress on the CSAC effort, including the development of custom vertical cavity surface emitting laser (VCSEL) sources and techniques for microfabricating miniature cesium vapor cells comprised of anodically bonded silicon and glass. Measurements of the signal contrast and linewidth of both the cesium D1 and D2 resonance transitions are compared, and frequency stability measurements of the CSAC testbed are presented.
We have undertaken a development effort to produce a prototype chip-scale atomic clock (CSAC). The design goals include short-term stability, with a total power consumption of less than 30 mW and overall device volume <1 cubic cm. The stringent power requirement dominates the physics package architecture, necessarily dictating a small volume gaseous atomic ensemble interrogated by a low-power semiconductor laser. At PTTI 2002 and PTTI 2003, we reported on laboratory experiments that underlie the fundamental architecture of our CSAC, based on interrogation of the cesium D1 transition by the technique of coherent population trapping (CPT). In the past year, the development effort has shifted from fundamental research and feasibility investigation to engineering and prototype development. In this paper, we report on the design of a rugged and compact physics package that is expected to exceed the ultimate performance and power requirements of the CSAC.
The spectroscopic technique of coherent population trapping (CPT) enables an all-optical interrogation of the groundstate hyperfine splitting of cesium (or rubidium), compared to the optical-microwave double resonance technique conventionally employed in atomic frequency standards. All-optical interrogation enables the reduction of the size and power consumption of an atomic clock by two orders of magnitude, and vertical-cavity surface-emitting lasers (VCSELs) are preferred optical sources due to their low power consumption and circular output beam. Several research teams are currently using VCSELs for DARPA's chip-scale atomic clock (CSAC) program with the goal of producing an atomic clock having a volume < 1 cm^3, a power consumption < 30 mW, and an instability (Allan deviation) < 1x10^-11 during a 1-hour averaging interval. This paper describes the VCSEL requirements for CPT-based atomic clocks, which include single mode operation, single polarization operation, modulation bandwidth > 4 GHz, low power consumption (for the CSAC), narrow linewidth, and low relative intensity noise (RIN). A significant manufacturing challenge is to reproducibly obtain the required wavelength at the specified VCSEL operating temperature and drive current. Data are presented that show the advantage of operating at the D1 (rather than D2) resonance of the alkali atoms. Measurements of VCSEL linewidth will be discussed in particular, since atomic clock performance is especially sensitive to this parameter.
We describe chip-scale batch-fabricated cesium cells utilizing semiconductor wafer processing, pin transfer of cesium, and silicon/Pyrex anodic bonding for cell sealing. Highspeed, single-mode linearly polarized VCSELs emitting at the 133Cs D1 line were fabricated, optimized for low threshold and high-speed operation with overall small power dissipation. Coherent population trapping (CPT) end-resonance signals with a contrast and linewidth of 5.4% and 7.1 kHz respectively are achieved using 1 mm optical path length cells and VCSEL driven with 1.25 mW RF modulation and 2.76 mW DC power dissipation. We demonstrate short-term stability with an atomic clock built with these components operating on the CPT end-resonance. The magnetic field is stabilized with a novel magnetic field locking scheme tapping the Zeeman resonance.
Ever since the idea of the chip-scale atomic clock (CSAC) based on coherent population trapping (CPT) transition theory was proposed, the CSAC has been used widely in many various fields because of its characteristics of low power consumption, small size and good performance. It can be used in micro-positioning navigation and timing system, geophysical prospecting of the ocean bottom, and 5G communication system. Researchers work on reducing its volume and power consumption to make it more widely used. In the meantime, we all made great effort to improve its long-term stability. In this paper, we report our progress toward chip-scale atomic clock based on the87Rb CPT transition during 2019. We reduced the volume of the CSAC from 20 cm3to 12 cm3. For the physical part, we optimized the structure of the physical package to make sure it is possible for mass production. For the electrical part, we redesigned and rearranged the circuit, optimized the temperature control algorithm, employed a disciplining method. Finally, the frequency stability of CSAC was obtained to be 3.66×10-11, 6.39×10-12and 3.42 ×10-13at the interrogation time of 1 s, 103s and 104s respectively.
Chip-scale atomic clocks are critical for applications requiring compact, energy-efficient, and highly stable timing, such as GPS receivers and communication systems. Coherent population trapping (CPT)-based atomic clocks, which commonly use vertical-cavity surface-emitting lasers (VCSELs), have enabled significant miniaturization. However, their precision is limited by the broad linewidth of VCSELs. Alternative laser technologies, such as distributed Bragg reflector lasers, distributed feedback lasers, and external cavity diode lasers (ECDLs), offer potential improvements but face challenges in achieving compact size and adequate modulation bandwidth. This study presents a 795 nm chip-ECDL with a direct modulation bandwidth up to 4 GHz, specifically designed for CPT chip-scale atomic clocks. Based on the chip-ECDL, a CPT atomic clock with a compact volume of 19.4 ml and power consumption of 1.5 W has been developed. Under identical operating conditions, the CPT signal produced by the chip-ECDL exhibits a 34% reduction in linewidth and a 1.14-fold increase in contrast compared to a VCSEL-based clock. Demonstrating short-term stability better than 5×10−11τ−1/2(1 s<τ<2000 s) and reaching a best stability of 6.6×10−13 at 2000 s, this work represents the application of an ECDL in a CPT chip-scale clock, advancing the development of next-generation, high-performance chip-scale atomic clocks.
An ultra-low power consumed chip-scale atomic clock (CSAC) based on rubidium 87 coherent population trapping (CPT) resonance was reported in this paper. During the previous year, we focused on the power consumption deduction and dedicated to improve the frequency stability simultaneously. The power consumption of physical package was dramatically dropped to 20 mW, and thus the total power consumed by the CSAC is below 160 mW. Long term frequency stability with 1.65×10-11at 100s., and 8.91×10-12at 1000s is obtained.