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Joint Conference of the IEEE International Frequency Control Symposium and International Symposium on Applications of Ferroelectrics (IFCS-ISAF)

Advances of Chip-Scale Atomic Clock in Peking University in 2019

Jianye Zhao, Ping Guo, Lin Dan, Hongling Meng

Published Jul 1, 2020• 2 citations

Abstract

Ever since the idea of the chip-scale atomic clock (CSAC) based on coherent population trapping (CPT) transition theory was proposed, the CSAC has been used widely in many various fields because of its characteristics of low power consumption, small size and good performance. It can be used in micro-positioning navigation and timing system, geophysical prospecting of the ocean bottom, and 5G communication system. Researchers work on reducing its volume and power consumption to make it more widely used. In the meantime, we all made great effort to improve its long-term stability. In this paper, we report our progress toward chip-scale atomic clock based on the87Rb CPT transition during 2019. We reduced the volume of the CSAC from 20 cm3to 12 cm3. For the physical part, we optimized the structure of the physical package to make sure it is possible for mass production. For the electrical part, we redesigned and rearranged the circuit, optimized the temperature control algorithm, employed a disciplining method. Finally, the frequency stability of CSAC was obtained to be 3.66×10-11, 6.39×10-12and 3.42 ×10-13at the interrogation time of 1 s, 103s and 104s respectively.

DOI: 10.1109/ifcs-isaf41089.2020.9234861

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Ever since the idea of the chip-scale atomic clock (CSAC) based on coherent population trapping (CPT) transition theory was proposed, the CSAC has been used widely in many various fields because of its characteristics of low power consumption, small size and good performance. It can be used in micro-positioning navigation and timing system, geophysical prospecting of the ocean bottom, and 5G communication system. Researchers work on reducing its volume and power consumption to make it more widely used. In the meantime, we all made great effort to improve its long-term stability. In this paper, we report our progress toward chip-scale atomic clock based on the87Rb CPT transition during 2019. We reduced the volume of the CSAC from 20 cm3to 12 cm3. For the physical part, we optimized the structure of the physical package to make sure it is possible for mass production. For the electrical part, we redesigned and rearranged the circuit, optimized the temperature control algorithm, employed a disciplining method. Finally, the frequency stability of CSAC was obtained to be 3.66×10-11, 6.39×10-12and 3.42 ×10-13at the interrogation time of 1 s, 103s and 104s respectively.

An ultra-low power consumed chip-scale atomic clock (CSAC) based on rubidium 87 coherent population trapping (CPT) resonance was reported in this paper. During the previous year, we focused on the power consumption deduction and dedicated to improve the frequency stability simultaneously. The power consumption of physical package was dramatically dropped to 20 mW, and thus the total power consumed by the CSAC is below 160 mW. Long term frequency stability with 1.65×10-11at 100s., and 8.91×10-12at 1000s is obtained.

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