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Joint Conference of the European Frequency and Time Forum and IEEE International Frequency Control Symposium (EFTF/IFCS)

Advances of chip-scale atomic clock in Peking University in 2015

Jianye Zhao, Yaolin Zhang, Shuangyou Zhang, Jianxiao Leng, Zhong Wang

Published May 1, 2016• 0 citations
Publisher

Abstract

In this paper we present our advance of chip-scale atomic clock (CSAC) based on the87Rb coherent population trap (CPT) transition. Compare with last year, we made great progress in frequency instabilities and power consumption. The overall size of the clock is 20 cm3volume and the total power consumption of the whole system is less than 350mW. Especially the frequency stability (Allan deviation) of the 10 MHz output signal reaches 6×10-12at average time of 1000 s.

DOI
10.1109/fcs.2016.7546753

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Ever since the idea of the chip-scale atomic clock (CSAC) based on coherent population trapping (CPT) transition theory was proposed, the CSAC has been used widely in many various fields because of its characteristics of low power consumption, small size and good performance. It can be used in micro-positioning navigation and timing system, geophysical prospecting of the ocean bottom, and 5G communication system. Researchers work on reducing its volume and power consumption to make it more widely used. In the meantime, we all made great effort to improve its long-term stability. In this paper, we report our progress toward chip-scale atomic clock based on the87Rb CPT transition during 2019. We reduced the volume of the CSAC from 20 cm3to 12 cm3. For the physical part, we optimized the structure of the physical package to make sure it is possible for mass production. For the electrical part, we redesigned and rearranged the circuit, optimized the temperature control algorithm, employed a disciplining method. Finally, the frequency stability of CSAC was obtained to be 3.66×10-11, 6.39×10-12and 3.42 ×10-13at the interrogation time of 1 s, 103s and 104s respectively.
We have undertaken the development of a chip-scale atomic clock (CSAC) whose design goals include short-term stability, sigma(sub y)(tau=1 hour), of 1x10(exp 11) with a total power consumption of 30 mW and an overall device volume of 1 cu cm. The stringent power requirement dominates the physics package architecture, dictating a small (<5 mm(exp 3) gaseous atomic ensemble interrogated by a low-power semiconductor laser. At PTTI 2002, we reported on initial experimental investigations leading to the decision to employ the coherent population trapping (CPT) interrogation technique. This paper describes our further progress on the CSAC effort, including the development of custom vertical cavity surface emitting laser (VCSEL) sources and techniques for microfabricating miniature cesium vapor cells comprised of anodically bonded silicon and glass. Measurements of the signal contrast and linewidth of both the cesium D1 and D2 resonance transitions are compared, and frequency stability measurements of the CSAC testbed are presented.