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The Chip-Scale Atomic Clock - Low-Power Physics Package

Robert Lutwak, Jinyi Deng, William Riley, Mathew K. Varghese, John LeBlanc, Gary Tepolt, Mark J. Mescher, Darwin K. Serkland, K.M. Geib, Gregory M. Peake

Published Dec 1, 2004• 64 citations
OpenAlex

Abstract

We have undertaken a development effort to produce a prototype chip-scale atomic clock (CSAC). The design goals include short-term stability, with a total power consumption of less than 30 mW and overall device volume <1 cubic cm. The stringent power requirement dominates the physics package architecture, necessarily dictating a small volume gaseous atomic ensemble interrogated by a low-power semiconductor laser. At PTTI 2002 and PTTI 2003, we reported on laboratory experiments that underlie the fundamental architecture of our CSAC, based on interrogation of the cesium D1 transition by the technique of coherent population trapping (CPT). In the past year, the development effort has shifted from fundamental research and feasibility investigation to engineering and prototype development. In this paper, we report on the design of a rugged and compact physics package that is expected to exceed the ultimate performance and power requirements of the CSAC.

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We have undertaken the development of a chip-scale atomic clock (CSAC) whose design goals include short-term stability, sigma(sub y)(tau=1 hour), of 1x10(exp 11) with a total power consumption of 30 mW and an overall device volume of 1 cu cm. The stringent power requirement dominates the physics package architecture, dictating a small (<5 mm(exp 3) gaseous atomic ensemble interrogated by a low-power semiconductor laser. At PTTI 2002, we reported on initial experimental investigations leading to the decision to employ the coherent population trapping (CPT) interrogation technique. This paper describes our further progress on the CSAC effort, including the development of custom vertical cavity surface emitting laser (VCSEL) sources and techniques for microfabricating miniature cesium vapor cells comprised of anodically bonded silicon and glass. Measurements of the signal contrast and linewidth of both the cesium D1 and D2 resonance transitions are compared, and frequency stability measurements of the CSAC testbed are presented.

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Ever since the idea of the chip-scale atomic clock (CSAC) based on coherent population trapping (CPT) transition theory was proposed, the CSAC has been used widely in many various fields because of its characteristics of low power consumption, small size and good performance. It can be used in micro-positioning navigation and timing system, geophysical prospecting of the ocean bottom, and 5G communication system. Researchers work on reducing its volume and power consumption to make it more widely used. In the meantime, we all made great effort to improve its long-term stability. In this paper, we report our progress toward chip-scale atomic clock based on the87Rb CPT transition during 2019. We reduced the volume of the CSAC from 20 cm3to 12 cm3. For the physical part, we optimized the structure of the physical package to make sure it is possible for mass production. For the electrical part, we redesigned and rearranged the circuit, optimized the temperature control algorithm, employed a disciplining method. Finally, the frequency stability of CSAC was obtained to be 3.66×10-11, 6.39×10-12and 3.42 ×10-13at the interrogation time of 1 s, 103s and 104s respectively.

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We have undertaken a development effort to produce a prototype chip-scale atomic clock (CSAC). The design goals include short-term stability, with a total power consumption of less than 30 mW and overall device volume <1 cubic cm. The stringent power requirement dominates the physics package architecture, necessarily dictating a small volume gaseous atomic ensemble interrogated by a low-power semiconductor laser. At PTTI 2002 and PTTI 2003, we reported on laboratory experiments that underlie the fundamental architecture of our CSAC, based on interrogation of the cesium D1 transition by the technique of coherent population trapping (CPT). In the past year, the development effort has shifted from fundamental research and feasibility investigation to engineering and prototype development. In this paper, we report on the design of a rugged and compact physics package that is expected to exceed the ultimate performance and power requirements of the CSAC.
We have undertaken the development of a chip-scale atomic clock (CSAC) whose design goals include short-term stability, sigma(sub y)(tau=1 hour), of 1x10(exp 11) with a total power consumption of 30 mW and an overall device volume of 1 cu cm. The stringent power requirement dominates the physics package architecture, dictating a small (<5 mm(exp 3) gaseous atomic ensemble interrogated by a low-power semiconductor laser. At PTTI 2002, we reported on initial experimental investigations leading to the decision to employ the coherent population trapping (CPT) interrogation technique. This paper describes our further progress on the CSAC effort, including the development of custom vertical cavity surface emitting laser (VCSEL) sources and techniques for microfabricating miniature cesium vapor cells comprised of anodically bonded silicon and glass. Measurements of the signal contrast and linewidth of both the cesium D1 and D2 resonance transitions are compared, and frequency stability measurements of the CSAC testbed are presented.
An ultra-low power consumed chip-scale atomic clock (CSAC) based on rubidium 87 coherent population trapping (CPT) resonance was reported in this paper. During the previous year, we focused on the power consumption deduction and dedicated to improve the frequency stability simultaneously. The power consumption of physical package was dramatically dropped to 20 mW, and thus the total power consumed by the CSAC is below 160 mW. Long term frequency stability with 1.65×10-11at 100s., and 8.91×10-12at 1000s is obtained.
The authors are developing chip-scale atomic clocks (CSACs) based on the85Rb coherent population trap (CPT) transition. As an intermediate milestone, we have developed a miniature atomic clock prototype. In this paper, we report on the design combing the miniature physics part, low-power digital control circuits and low-power microwave system, and the process that enable an atomic clock to be made with an overall size of 20 cm3volume, power consumption about 400 mWatts, and an Allen Deviation at 100 s of 2.9E-11.
Ever since the idea of the chip-scale atomic clock (CSAC) based on coherent population trapping (CPT) transition theory was proposed, the CSAC has been used widely in many various fields because of its characteristics of low power consumption, small size and good performance. It can be used in micro-positioning navigation and timing system, geophysical prospecting of the ocean bottom, and 5G communication system. Researchers work on reducing its volume and power consumption to make it more widely used. In the meantime, we all made great effort to improve its long-term stability. In this paper, we report our progress toward chip-scale atomic clock based on the87Rb CPT transition during 2019. We reduced the volume of the CSAC from 20 cm3to 12 cm3. For the physical part, we optimized the structure of the physical package to make sure it is possible for mass production. For the electrical part, we redesigned and rearranged the circuit, optimized the temperature control algorithm, employed a disciplining method. Finally, the frequency stability of CSAC was obtained to be 3.66×10-11, 6.39×10-12and 3.42 ×10-13at the interrogation time of 1 s, 103s and 104s respectively.
Symmetricom-TRC has undertaken a development effort to produce a prototype chip-scale atomic clock "CSAC". The overall architecture of the CSAC and, in particular, the physics package, must be defined early in the project, prior to the onset of a large-scale engineering effort. Within the constraints imposed by the performance goals of the project, we have recognized two possible schemes for interrogating the ground-state hyperfine frequency of the gaseous atomic ensemble: the conventional double-resonance technique and the coherent population trapping technique. In this paper, we describe a laboratory apparatus, which allows for in situ comparison of the two techniques, without the ambiguities associated with comparing data from disparate experiments. Data are presented comparing the short-term stability resultant of the two techniques, as well as environmental sensitivity to resonance cell temperature, laser intensity, and RF power.
Research on chip-scale atomic clocks (CSACs) based on coherent population trapping (CPT) is reviewed. The background and the inspiration for the research are described, including the important schemes proposed to improve the CPT signal quality, the selection of atoms and buffer gases, and the development of micro-cell fabrication. With regard to the reliability, stability, and service life of the CSACs, the research regarding the sensitivity of the CPT resonance to temperature and laser power changes is also reviewed, as well as the CPT resonance's collision and light of frequency shifts. The first generation CSACs have already been developed but its characters are still far from our expectations. Our conclusion is that miniaturization and power reduction are the most important aspects calling for further research.