IEICE Technical Report; IEICE Tech. Rep.
Optimization of a Josephson latching driver using 10-kA/cm2 Nb process for a Josephson-CMOS hybrid memory
Yuki Hironaka, Yuki Yamanashi, Nobuyuki Yoshikawa
IEICE Technical Report; IEICE Tech. Rep.
Yuki Hironaka, Yuki Yamanashi, Nobuyuki Yoshikawa