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Physica C Superconductivity

Parameter optimization of a Josephson latching driver based on bit-error-rate simulations

Hayate Kojima, Y. Yamashiro, K. Fujiwara, Nobuyuki Yoshikawa, Akira Fujimaki, Hirotaka Terai, Shinichi Yorozu

Published Jul 26, 2005• 2 citations
Publisher
DOI
10.1016/j.physc.2005.03.068

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A new Josephson latching driver with a current-injection device at an input port has been developed and tested. It has high input sensitivity and a wide bias margin. Under an optimal bias condition, the bit-error rate (BER) of this driver is below 10/sup -12/ at data rates of 5 and 10 Gb/s. The driver can be switched by superconducting single-flux quantum (SFQ) pulse input and can be used as an amplifier to test the BER of SFQ circuits. In such a test, the BER of an SFQ converter operating at 5 Gb/s was less than 10/sup -12/ with bias margin of /spl plusmn/20%.
In this study, we designed, fabricated, and experimentally tested a Josephson latching driver (JLD), a superconductor-to-semiconductor interface circuit for use in Josephson-CMOS hybrid memory, utilizing a 10-kA/cm2Nb process. The JLD is composed of a voltage driver known as a Suzuki stack and a Josephson four-junction logic (4JL) gate that serves as a preamplifier. The basic structure is based on our previous design using the 2.5-kA/cm2Nb process. In this study, we optimized the critical current and the load resistance of the 4JL gate, taking into account the parameters of the Josephson junctions in the 10-kA/cm2process. In experiments with the fabricated test circuit, we confirmed the correct operation of the JLD (bit error rate−11) at a target frequency of 5 GHz. We also confirmed the correct function of multichannel JLDs, which were used as interface circuits in Josephson-CMOS hybrid memory, in a low-frequency test.