Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Transactions on Applied Superconductivity

Josephson Latching Driver With a Low Bit-Error Rate

N. Harada, Nobuyuki Yoshikawa, Akira Yoshida, Naoki Yokoyama

Published Nov 30, 2004• 9 citations
Publisher

Abstract

A new Josephson latching driver with a current-injection device at an input port has been developed and tested. It has high input sensitivity and a wide bias margin. Under an optimal bias condition, the bit-error rate (BER) of this driver is below 10/sup -12/ at data rates of 5 and 10 Gb/s. The driver can be switched by superconducting single-flux quantum (SFQ) pulse input and can be used as an amplifier to test the BER of SFQ circuits. In such a test, the BER of an SFQ converter operating at 5 Gb/s was less than 10/sup -12/ with bias margin of /spl plusmn/20%.

DOI
10.1109/tasc.2004.837112

Related papers

High-speed demonstration of an output interface driver for single-flux quantum systems

N. Harada, Akira Yoshida, Naoki Yokoyama

The high-speed operation of a one-channel output interface for a single-flux quantum (SFQ) system has been demonstrated. The interface consisted of a Josephson latching driver, a room-temperature semiconductor amplifier, and a decision circuit module. The Josephson latching driver was fabricated by using a 2.5-kA/cm/sup 2/ standard Nb junction process and used to amplify an SFQ pulse into a 5.5-mV level signal at 10 Gb/s. The interface converted the SFQ pulse signal into a nonreturn-to-zero signal having an amplitude of 1 V at 10 Gb/s.

IEEE Transactions on Applied Superconductivity•Sep 1, 2002•9 citations

A High-Speed Interface Based on a Josephson Latching Driver for Adiabatic Quantum-Flux-Parametron Logic

Fumihiro China, Naoki Takeuchi, Hideo Suzuki +3 more

The adiabatic quantum flux parametron (AQFP) is an energy-efficient, high-speed superconducting logic device. To observe the tiny output currents from the AQFP in experiments, high-speed voltage drivers are indispensable. In the present study, we develop a compact voltage driver for AQFP logic based on a Josephson latching driver (JLD), which has been used as a high-speed driver for rapid single-flux-quantum (RSFQ) logic. In the JLD-based voltage driver, the signal currents of AQFP gates are converted into gap-voltage-level signals via an AQFP/RSFQ interface and a four-junction logic gate. Furthermore, this voltage driver includes only 15 Josephson junctions, which is much fewer than in the case for the previously designed driver based on dc superconducting quantum interference devices (60 junctions). In measurement, we successfully operate the JLD-based voltage driver up to 4 GHz. We also evaluate the bit error rate (BER) of the driver and find that the BER is 7.92×10-10 and 2.67×10-3 at 1GHz and 4GHz, respectively.

IEICE Transactions on Electronics•Dec 2, 2021•3 citations

Output Interface With Latching Driver for LTS-SFQ Circuits

Tsunehiro Hato, Masahiro Horibe, H. Wakana +2 more

We propose an output interface with a latching driver for single-flux-quantum (SFQ) circuits operating at 4.2 K. An optimum critical current density J/sub c/ of the latching driver was discussed, and a multichip module (MCM) structure with SFQ circuits and latching drivers was proposed for 40-Gb/s operation. To optimize J/sub c/ of the latching driver, we calculated the punchthrough probability of Nb-Al-AlO/sub x/-Nb junctions and high-temperature superconductor (HTS) junctions. The Nb junction with a J/sub c/ of 45 kA/cm/sup 2/, which has a hysteresis of 44% for the latching operation, leads to a punchthrough probability lower than 10/sup -15/ for an ideal ac-bias of 40 GHz. On the other hand, ramp-edge-type interface-modified junctions based on YBa/sub 2/Cu/sub 3/O/sub 7-x/ have an optimum J/sub c/ of 60 kA/cm/sup 2/ that gives the smallest punchthrough probability lower than 10/sup -15/ for an ideal ac-bias of 40 GHz without any shunt capacitance. Because the optimum J/sub c/ of 45 kA/cm/sup 2/ for the latching driver is too large to fabricate large-scale integrated SFQ circuits with the Nb junction, the MCM structure consisting of SFQ circuits and latching drivers with the optimum J/sub c/ is important to prepare 40-Gb/s SFQ systems. The J/sub c/ of 60 kA/cm/sup 2/ is a practical value for the HTS junctions, and use of the low-temperature superconductor (LTS)-HTS MCM structure is also one way to realize the high-speed SFQ systems.

IEEE Transactions on Applied Superconductivity•Mar 1, 2005•5 citations

Logic operation at 5 gb/s of an output interface for single-flux-quantum systems

N. Harada, Nobuyuki Yoshikawa, K. Yoda +2 more

High-speed logic operation of an output interface circuit for a single-flux-quantum (SFQ) system was demonstrated at a data rate of 5 Gb/s. Using NEC's 2.5-kA/cm/sup 2/ Nb junction process, we designed, fabricated, and tested the interface circuit consisting of a 2-b SFQ demultiplexer and two Josephson latching drivers. We verified the proper operation of the demultiplexer. The interface can convert 5-Gb/s SFQ-pulse data into two-channel 2.5-Gb/s return-to-zero data with an amplitude of approximately 6 mV.

IEEE Transactions on Applied Superconductivity•Sep 1, 2003•3 citations

SFQ-to-level logic conversion by HTS Josephson drivers for output interface

Tsunehiro Hato, Yoshihiro Ishimaru, N. Harada +5 more

Latching-type driver circuits integrated with high-temperature superconductivity (HTS) junctions and two types of resistor were fabricated. These circuits could successfully perform latching operation by means of a single-flux-quantum (SFQ) signal input. Ramp-edge-type HTS junctions were fabricated by interface engineering and showed a hysteretic current-voltage characteristics under a temperature of 50 K. The critical current (I/sub c/) of these 5-micron-wide junctions was about 0.2 mA and the I/sub c/R/sub n/ product was about 1.7 mV at 4.2 K. The circuits included two types of resistors, which were made of RF-magnetron-sputtered indium-tin-oxide (ITO) and Au films. A driver with a parallel 2-junction-stack could convert an SFQ pulse, which was transformed through several Josephson transmission lines (JTL's) from a DC/SFQ circuit, to a 2.3-mV level signal.

IEEE Transactions on Applied Superconductivity•Jun 1, 2003•8 citations

A novel approach to chip-to-chip communication using a single flux quantum pulse

Masaaki Maezawa, Hirotake Yamamori, Alexandre Shoji

A novel approach to chip-to-chip communication for RSFQ technology is proposed. The main idea is to fabricate Josephson junctions on a substrate for multi-chip packaging, which equips the substrate as well as the chip with built-in active drivers and receivers. The driver on the chip is connected directly to the receiver on the substrate through a connector which can be considered as a lumped circuit element. Because the circuit is free from the impedance matching constraint, broadband chip-to-chip data transfer with wide operating margins will be realized. We have designed, simulated and optimized a chip-to-chip single flux quantum (SFQ) pulse transfer circuit. For a connector inductance of 20 pH, the bias current margins and the maximum throughput have been calculated to be /spl plusmn/24% and above 50 Gb/s, respectively.

IEEE Transactions on Applied Superconductivity•Jun 1, 1999•8 citations
A new Josephson latching driver with a current-injection device at an input port has been developed and tested. It has high input sensitivity and a wide bias margin. Under an optimal bias condition, the bit-error rate (BER) of this driver is below 10/sup -12/ at data rates of 5 and 10 Gb/s. The driver can be switched by superconducting single-flux quantum (SFQ) pulse input and can be used as an amplifier to test the BER of SFQ circuits. In such a test, the BER of an SFQ converter operating at 5 Gb/s was less than 10/sup -12/ with bias margin of /spl plusmn/20%.
The high-speed operation of a one-channel output interface for a single-flux quantum (SFQ) system has been demonstrated. The interface consisted of a Josephson latching driver, a room-temperature semiconductor amplifier, and a decision circuit module. The Josephson latching driver was fabricated by using a 2.5-kA/cm/sup 2/ standard Nb junction process and used to amplify an SFQ pulse into a 5.5-mV level signal at 10 Gb/s. The interface converted the SFQ pulse signal into a nonreturn-to-zero signal having an amplitude of 1 V at 10 Gb/s.
The adiabatic quantum flux parametron (AQFP) is an energy-efficient, high-speed superconducting logic device. To observe the tiny output currents from the AQFP in experiments, high-speed voltage drivers are indispensable. In the present study, we develop a compact voltage driver for AQFP logic based on a Josephson latching driver (JLD), which has been used as a high-speed driver for rapid single-flux-quantum (RSFQ) logic. In the JLD-based voltage driver, the signal currents of AQFP gates are converted into gap-voltage-level signals via an AQFP/RSFQ interface and a four-junction logic gate. Furthermore, this voltage driver includes only 15 Josephson junctions, which is much fewer than in the case for the previously designed driver based on dc superconducting quantum interference devices (60 junctions). In measurement, we successfully operate the JLD-based voltage driver up to 4 GHz. We also evaluate the bit error rate (BER) of the driver and find that the BER is 7.92×10-10 and 2.67×10-3 at 1GHz and 4GHz, respectively.
We propose an output interface with a latching driver for single-flux-quantum (SFQ) circuits operating at 4.2 K. An optimum critical current density J/sub c/ of the latching driver was discussed, and a multichip module (MCM) structure with SFQ circuits and latching drivers was proposed for 40-Gb/s operation. To optimize J/sub c/ of the latching driver, we calculated the punchthrough probability of Nb-Al-AlO/sub x/-Nb junctions and high-temperature superconductor (HTS) junctions. The Nb junction with a J/sub c/ of 45 kA/cm/sup 2/, which has a hysteresis of 44% for the latching operation, leads to a punchthrough probability lower than 10/sup -15/ for an ideal ac-bias of 40 GHz. On the other hand, ramp-edge-type interface-modified junctions based on YBa/sub 2/Cu/sub 3/O/sub 7-x/ have an optimum J/sub c/ of 60 kA/cm/sup 2/ that gives the smallest punchthrough probability lower than 10/sup -15/ for an ideal ac-bias of 40 GHz without any shunt capacitance. Because the optimum J/sub c/ of 45 kA/cm/sup 2/ for the latching driver is too large to fabricate large-scale integrated SFQ circuits with the Nb junction, the MCM structure consisting of SFQ circuits and latching drivers with the optimum J/sub c/ is important to prepare 40-Gb/s SFQ systems. The J/sub c/ of 60 kA/cm/sup 2/ is a practical value for the HTS junctions, and use of the low-temperature superconductor (LTS)-HTS MCM structure is also one way to realize the high-speed SFQ systems.
High-speed logic operation of an output interface circuit for a single-flux-quantum (SFQ) system was demonstrated at a data rate of 5 Gb/s. Using NEC's 2.5-kA/cm/sup 2/ Nb junction process, we designed, fabricated, and tested the interface circuit consisting of a 2-b SFQ demultiplexer and two Josephson latching drivers. We verified the proper operation of the demultiplexer. The interface can convert 5-Gb/s SFQ-pulse data into two-channel 2.5-Gb/s return-to-zero data with an amplitude of approximately 6 mV.
Latching-type driver circuits integrated with high-temperature superconductivity (HTS) junctions and two types of resistor were fabricated. These circuits could successfully perform latching operation by means of a single-flux-quantum (SFQ) signal input. Ramp-edge-type HTS junctions were fabricated by interface engineering and showed a hysteretic current-voltage characteristics under a temperature of 50 K. The critical current (I/sub c/) of these 5-micron-wide junctions was about 0.2 mA and the I/sub c/R/sub n/ product was about 1.7 mV at 4.2 K. The circuits included two types of resistors, which were made of RF-magnetron-sputtered indium-tin-oxide (ITO) and Au films. A driver with a parallel 2-junction-stack could convert an SFQ pulse, which was transformed through several Josephson transmission lines (JTL's) from a DC/SFQ circuit, to a 2.3-mV level signal.
A novel approach to chip-to-chip communication for RSFQ technology is proposed. The main idea is to fabricate Josephson junctions on a substrate for multi-chip packaging, which equips the substrate as well as the chip with built-in active drivers and receivers. The driver on the chip is connected directly to the receiver on the substrate through a connector which can be considered as a lumped circuit element. Because the circuit is free from the impedance matching constraint, broadband chip-to-chip data transfer with wide operating margins will be realized. We have designed, simulated and optimized a chip-to-chip single flux quantum (SFQ) pulse transfer circuit. For a connector inductance of 20 pH, the bias current margins and the maximum throughput have been calculated to be /spl plusmn/24% and above 50 Gb/s, respectively.