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IEEE Transactions on Applied Superconductivity

Logic operation at 5 gb/s of an output interface for single-flux-quantum systems

N. Harada, Nobuyuki Yoshikawa, K. Yoda, Akira Yoshida, Naoki Yokoyama

Published Sep 1, 2003• 3 citations
Publisher

Abstract

High-speed logic operation of an output interface circuit for a single-flux-quantum (SFQ) system was demonstrated at a data rate of 5 Gb/s. Using NEC's 2.5-kA/cm/sup 2/ Nb junction process, we designed, fabricated, and tested the interface circuit consisting of a 2-b SFQ demultiplexer and two Josephson latching drivers. We verified the proper operation of the demultiplexer. The interface can convert 5-Gb/s SFQ-pulse data into two-channel 2.5-Gb/s return-to-zero data with an amplitude of approximately 6 mV.

DOI
10.1109/tasc.2003.816901

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IEEE Transactions on Applied Superconductivity•Jun 1, 2003•8 citations
High-speed logic operation of an output interface circuit for a single-flux-quantum (SFQ) system was demonstrated at a data rate of 5 Gb/s. Using NEC's 2.5-kA/cm/sup 2/ Nb junction process, we designed, fabricated, and tested the interface circuit consisting of a 2-b SFQ demultiplexer and two Josephson latching drivers. We verified the proper operation of the demultiplexer. The interface can convert 5-Gb/s SFQ-pulse data into two-channel 2.5-Gb/s return-to-zero data with an amplitude of approximately 6 mV.
The high-speed operation of a one-channel output interface for a single-flux quantum (SFQ) system has been demonstrated. The interface consisted of a Josephson latching driver, a room-temperature semiconductor amplifier, and a decision circuit module. The Josephson latching driver was fabricated by using a 2.5-kA/cm/sup 2/ standard Nb junction process and used to amplify an SFQ pulse into a 5.5-mV level signal at 10 Gb/s. The interface converted the SFQ pulse signal into a nonreturn-to-zero signal having an amplitude of 1 V at 10 Gb/s.
We propose an output interface with a latching driver for single-flux-quantum (SFQ) circuits operating at 4.2 K. An optimum critical current density J/sub c/ of the latching driver was discussed, and a multichip module (MCM) structure with SFQ circuits and latching drivers was proposed for 40-Gb/s operation. To optimize J/sub c/ of the latching driver, we calculated the punchthrough probability of Nb-Al-AlO/sub x/-Nb junctions and high-temperature superconductor (HTS) junctions. The Nb junction with a J/sub c/ of 45 kA/cm/sup 2/, which has a hysteresis of 44% for the latching operation, leads to a punchthrough probability lower than 10/sup -15/ for an ideal ac-bias of 40 GHz. On the other hand, ramp-edge-type interface-modified junctions based on YBa/sub 2/Cu/sub 3/O/sub 7-x/ have an optimum J/sub c/ of 60 kA/cm/sup 2/ that gives the smallest punchthrough probability lower than 10/sup -15/ for an ideal ac-bias of 40 GHz without any shunt capacitance. Because the optimum J/sub c/ of 45 kA/cm/sup 2/ for the latching driver is too large to fabricate large-scale integrated SFQ circuits with the Nb junction, the MCM structure consisting of SFQ circuits and latching drivers with the optimum J/sub c/ is important to prepare 40-Gb/s SFQ systems. The J/sub c/ of 60 kA/cm/sup 2/ is a practical value for the HTS junctions, and use of the low-temperature superconductor (LTS)-HTS MCM structure is also one way to realize the high-speed SFQ systems.
Many applications of Single-Flux-Quantum (SFQ) circuits will rely on the transfer of multi-Gigabit per second data streams from SFQ logic to semiconductor logic for further processing. The low output voltages of superconducting circuits currently limit the data rate per channel to a few GHz. We have designed and fabricated an SFQ demultiplexer to reduce data transfer clock rates. The demultiplexer uses clocked data distribution through a binary tree architecture. The circuit was fabricated using an eight level Nb/AlO/sub x//Nb process and tested at 4.2 K.
Single-flux-quantum (SFQ) technology is a novel technology where binary information is represented by a single flux. It enables us to realize high-speed, low-power SFQ logic circuits, surpassing conventional complementary metal-oxide-silicon (CMOS) technology. We proposed an SFQ packet switch to avoid the bottlenecks in broadband networks of the future. To demonstrate high-speed operation of an SFQ logic circuit and its application to our switch architecture, we designed a cross/bar switch. It consists of 13 logic gates and 581 Josephson junctions were used in the layout. We confirmed correct operations up to 33 GHz in simulation. We placed the switch circuit in an on-chip test system for high-speed (over 10 GHz) test. Including I/O circuits, the system as a whole consists of 1236 Josephson junctions. The chip was fabricated by using NEC's standard Nb process. We carried out an on-chip test and found correct operations up to 35 GHz.
Latching-type driver circuits integrated with high-temperature superconductivity (HTS) junctions and two types of resistor were fabricated. These circuits could successfully perform latching operation by means of a single-flux-quantum (SFQ) signal input. Ramp-edge-type HTS junctions were fabricated by interface engineering and showed a hysteretic current-voltage characteristics under a temperature of 50 K. The critical current (I/sub c/) of these 5-micron-wide junctions was about 0.2 mA and the I/sub c/R/sub n/ product was about 1.7 mV at 4.2 K. The circuits included two types of resistors, which were made of RF-magnetron-sputtered indium-tin-oxide (ITO) and Au films. A driver with a parallel 2-junction-stack could convert an SFQ pulse, which was transformed through several Josephson transmission lines (JTL's) from a DC/SFQ circuit, to a 2.3-mV level signal.