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Japanese Journal of Applied Physics

A High-Speed Josephson Latching Driver for a Superconducting Single-Flux-Quantum System to Semiconductor System Interface

Naoki Harada, Akira Yoshida, Naoki Yokoyama

Published Nov 1, 2000• 8 citations
Publisher

Abstract

We have used a 2.5 kA/cm2 standard Nb junction technique to fabricate superconducting driver circuits and here present experimental results. The driver consists of 16 resistively shunted stacked junctions and an input junction. It is capable of converting a single flux quantum pulse to 10 mV at 3 GHz, and 7 mV at 10 GHz. The driver is thus a potential high-speed output interface between superconducting single-flux-guantum (SFQ) systems and room-temperature semiconductor systems.

DOI
10.1143/jjap.39.l1158

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IEEE Transactions on Applied Superconductivity•Mar 1, 2005•5 citations
We have used a 2.5 kA/cm2 standard Nb junction technique to fabricate superconducting driver circuits and here present experimental results. The driver consists of 16 resistively shunted stacked junctions and an input junction. It is capable of converting a single flux quantum pulse to 10 mV at 3 GHz, and 7 mV at 10 GHz. The driver is thus a potential high-speed output interface between superconducting single-flux-guantum (SFQ) systems and room-temperature semiconductor systems.
The high-speed operation of a one-channel output interface for a single-flux quantum (SFQ) system has been demonstrated. The interface consisted of a Josephson latching driver, a room-temperature semiconductor amplifier, and a decision circuit module. The Josephson latching driver was fabricated by using a 2.5-kA/cm/sup 2/ standard Nb junction process and used to amplify an SFQ pulse into a 5.5-mV level signal at 10 Gb/s. The interface converted the SFQ pulse signal into a nonreturn-to-zero signal having an amplitude of 1 V at 10 Gb/s.
We report on a latching-type driver operated at 30 K for the output interface of single-flux-quantum (SFQ) circuits. Ramp-edge-type high-temperature superconductor (HTS) junctions showed only small inherent hysteresis in current–voltage characteristics at a temperature of 30 K. To have hysteresis large enough for latching operation, we chose La-doped YbBaCuO as a counter electrode of an interface modified junction, and used amorphous LaSrAlTaO to form an additional barrier to the interface modified barrier. The junction shunted with optimized capacitance showed sufficiently large hysteresis of 33%, which is as large as that of a non-shunted junction at 4.2 K. We employed 20 kA cm−2 as the critical current density (Jc) of the junction to fabricate dc/SFQ, Josephson transmission lines (JTLs) and the latching driver on the same chip. It is smaller than the optimum current density that gives the smallest punchthrough probability of the junction, which was calculated to be 10−12 for a 30 Gbps ac bias by using the junction parameters at 30 K. However, the probability for Jc of 20 kA cm−2 is still smaller than that of low-temperature semiconductor junctions because of the larger Jc of the HTS junctions. The fabricated latching driver successfully converted the SFQ pulse, which passed through several JTLs from the dc/SFQ circuit, to a 1 mV level signal at 30 K.
We developed a latching-type driver using capacitively shunted high-temperature superconductivity (HTS) junctions for Single-Flux-Quantum (SFQ)-semiconductor output interfaces and fabricated it using ramp-edge-type HTS junctions. Assuming a junction IcRn product of 2 mV, a circuit simulation shows that the driver can produce an output of about 8 mV from an SFQ input pulse with a sufficiently short rise time for an interface clock operation of several gigahertz. HTS junctions were fabricated using the interface engineering method, and capacitors were made from an Indium oxide insulator (the dielectric constant was about 23 at 20 K) sandwiched by YBa/sub 2/Cu/sub 3/O/sub 7-x/ (YBCO) electrodes. The hysteresis of the I-V characteristics of the junctions increased by increasing the area of capacitance. The latching operation of the driver was observed with an output voltage of up to 3 mV.
Latching-type driver circuits integrated with high-temperature superconductivity (HTS) junctions and two types of resistor were fabricated. These circuits could successfully perform latching operation by means of a single-flux-quantum (SFQ) signal input. Ramp-edge-type HTS junctions were fabricated by interface engineering and showed a hysteretic current-voltage characteristics under a temperature of 50 K. The critical current (I/sub c/) of these 5-micron-wide junctions was about 0.2 mA and the I/sub c/R/sub n/ product was about 1.7 mV at 4.2 K. The circuits included two types of resistors, which were made of RF-magnetron-sputtered indium-tin-oxide (ITO) and Au films. A driver with a parallel 2-junction-stack could convert an SFQ pulse, which was transformed through several Josephson transmission lines (JTL's) from a DC/SFQ circuit, to a 2.3-mV level signal.
High-speed logic operation of an output interface circuit for a single-flux-quantum (SFQ) system was demonstrated at a data rate of 5 Gb/s. Using NEC's 2.5-kA/cm/sup 2/ Nb junction process, we designed, fabricated, and tested the interface circuit consisting of a 2-b SFQ demultiplexer and two Josephson latching drivers. We verified the proper operation of the demultiplexer. The interface can convert 5-Gb/s SFQ-pulse data into two-channel 2.5-Gb/s return-to-zero data with an amplitude of approximately 6 mV.
We propose an output interface with a latching driver for single-flux-quantum (SFQ) circuits operating at 4.2 K. An optimum critical current density J/sub c/ of the latching driver was discussed, and a multichip module (MCM) structure with SFQ circuits and latching drivers was proposed for 40-Gb/s operation. To optimize J/sub c/ of the latching driver, we calculated the punchthrough probability of Nb-Al-AlO/sub x/-Nb junctions and high-temperature superconductor (HTS) junctions. The Nb junction with a J/sub c/ of 45 kA/cm/sup 2/, which has a hysteresis of 44% for the latching operation, leads to a punchthrough probability lower than 10/sup -15/ for an ideal ac-bias of 40 GHz. On the other hand, ramp-edge-type interface-modified junctions based on YBa/sub 2/Cu/sub 3/O/sub 7-x/ have an optimum J/sub c/ of 60 kA/cm/sup 2/ that gives the smallest punchthrough probability lower than 10/sup -15/ for an ideal ac-bias of 40 GHz without any shunt capacitance. Because the optimum J/sub c/ of 45 kA/cm/sup 2/ for the latching driver is too large to fabricate large-scale integrated SFQ circuits with the Nb junction, the MCM structure consisting of SFQ circuits and latching drivers with the optimum J/sub c/ is important to prepare 40-Gb/s SFQ systems. The J/sub c/ of 60 kA/cm/sup 2/ is a practical value for the HTS junctions, and use of the low-temperature superconductor (LTS)-HTS MCM structure is also one way to realize the high-speed SFQ systems.