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IEEE Transactions on Applied Superconductivity

A single-flux-quantum demultiplexer

Donald L. Miller, John X. Przybysz, A. Hodge Worsham, Joonhee Kang

Published Jun 1, 1997• 14 citations
Publisher

Abstract

Many applications of Single-Flux-Quantum (SFQ) circuits will rely on the transfer of multi-Gigabit per second data streams from SFQ logic to semiconductor logic for further processing. The low output voltages of superconducting circuits currently limit the data rate per channel to a few GHz. We have designed and fabricated an SFQ demultiplexer to reduce data transfer clock rates. The demultiplexer uses clocked data distribution through a binary tree architecture. The circuit was fabricated using an eight level Nb/AlO/sub x//Nb process and tested at 4.2 K.

DOI
10.1109/77.621793

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IEEE Transactions on Applied Superconductivity•Jun 1, 1995•28 citations
Many applications of Single-Flux-Quantum (SFQ) circuits will rely on the transfer of multi-Gigabit per second data streams from SFQ logic to semiconductor logic for further processing. The low output voltages of superconducting circuits currently limit the data rate per channel to a few GHz. We have designed and fabricated an SFQ demultiplexer to reduce data transfer clock rates. The demultiplexer uses clocked data distribution through a binary tree architecture. The circuit was fabricated using an eight level Nb/AlO/sub x//Nb process and tested at 4.2 K.
High-speed logic operation of an output interface circuit for a single-flux-quantum (SFQ) system was demonstrated at a data rate of 5 Gb/s. Using NEC's 2.5-kA/cm/sup 2/ Nb junction process, we designed, fabricated, and tested the interface circuit consisting of a 2-b SFQ demultiplexer and two Josephson latching drivers. We verified the proper operation of the demultiplexer. The interface can convert 5-Gb/s SFQ-pulse data into two-channel 2.5-Gb/s return-to-zero data with an amplitude of approximately 6 mV.
A 1-to-4 demultiplexer (DEMUX) was designed based on Single Flux Quantum (SFQ) circuitry and high-speed operation was confirmed using on-chip testing. The circuit was designed with a binary-tree structure to enable high-speed operation. We also investigated timing between clock and data signals in detail. Monte Carlo simulation was applied to vary the design parameters pseudo-randomly and the spread of timing was obtained by circuit simulation. Even if the circuit parameters varied as a result of the fabrication process, proper timing was maintained by optimizing the length of Josephson transmission line. The 1-to-4 DEMUX we fabricated distributed data signals correctly at operating frequencies up to 56 GHz with a bias margin of /spl plusmn/7%.
A demultiplexer (DMUX) is a key subsystem of rapid single flux quantum (RSFQ) circuits and systems in practical applications. High-speed data from RSFQ circuits should be converted into sufficiently low-speed ones for transmission to and processing by room temperature electronics. We designed, fabricated and successfully tested an RSFQ DMUX based on the synchronous shift-and-dump architecture whose advantages are modularity and compactness. A 1-to-8 DMUX was implemented using our standard cell library on 1.6 kA cm −2 Nb trilayer technology. Fully functional operation was confirmed by low speed testing. Experimental bias margins were as large as ±16%. Results of average voltage measurements implied that the DMUX was operated at data rates up to 25 Gb s −1 .
Single-flux-quantum (SFQ) technology is a novel technology where binary information is represented by a single flux. It enables us to realize high-speed, low-power SFQ logic circuits, surpassing conventional complementary metal-oxide-silicon (CMOS) technology. We proposed an SFQ packet switch to avoid the bottlenecks in broadband networks of the future. To demonstrate high-speed operation of an SFQ logic circuit and its application to our switch architecture, we designed a cross/bar switch. It consists of 13 logic gates and 581 Josephson junctions were used in the layout. We confirmed correct operations up to 33 GHz in simulation. We placed the switch circuit in an on-chip test system for high-speed (over 10 GHz) test. Including I/O circuits, the system as a whole consists of 1236 Josephson junctions. The chip was fabricated by using NEC's standard Nb process. We carried out an on-chip test and found correct operations up to 35 GHz.
Interface circuits for the transfer of data between Single Flux Quantum (SPQ) circuits have been designed, fabricated, and operated at speeds up to 3 Gigabits per second. The circuit employed an improved version of the SFQ/Latch converter, a Modified Variable Threshold Logic (MVTL) OR/AND gate, a 3/spl times/ latching amplifier, and a 3/spl times/-to-10/spl times/ latching amplifier. The amplifier circuits employed stacks of latching junctions. Resistors between the parallel stacks of junctions damped residual currents to prevent flux trapping during reset. Tolerance to critical current variations in the series stacks of junctions was provided by inductive chokes on the input junction shunting resistors. Microwave modeling programs were used to ensure proper distribution of the applied current to all of the latching elements. The circuit transferred data at 3 Gigabits per second from one SFQ circuit up to room temperature and back to another SFQ circuit through 3.4 meters of 50-ohm cable.
We describe the design of a fast single-flux-quantum decoder which can be used, e.g., in fast RAMs, general-purpose microprocessors, and communication channel switches. The core of the circuit is a tree of the single-bit SFQ demultiplexer with toggle (rather than the reset-set) control. Three new RSFQ cells: the demultiplexer, D flip-flop with complementary outputs, and serial XOR with large parameter tolerances (dc bias margins of /spl plusmn/25%, /spl plusmn/26%, and /spl plusmn/27%, respectively) have been developed for the decoder project. We have designed the first 16-bit prototype of the decoder for 1-kA/cm/sup 2/ niobium-trilayer technology and tested it at low frequencies. The circuit was completely operable except for 3 (of 16) output SFQ/DC converters. Simulations show that the circuit should allow data rate in excess of 60 Gbit/s and channel switching time below 20 ps.>