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IEEE Transactions on Applied Superconductivity

Interface circuits for chip-to-chip data transfer at GHz rates

John X. Przybysz, Donald L. Miller, S.S. Martinet, Joonhee Kang, A. Hodge Worsham, M.L. Farich

Published Jun 1, 1997• 27 citations

Abstract

Interface circuits for the transfer of data between Single Flux Quantum (SPQ) circuits have been designed, fabricated, and operated at speeds up to 3 Gigabits per second. The circuit employed an improved version of the SFQ/Latch converter, a Modified Variable Threshold Logic (MVTL) OR/AND gate, a 3/spl times/ latching amplifier, and a 3/spl times/-to-10/spl times/ latching amplifier. The amplifier circuits employed stacks of latching junctions. Resistors between the parallel stacks of junctions damped residual currents to prevent flux trapping during reset. Tolerance to critical current variations in the series stacks of junctions was provided by inductive chokes on the input junction shunting resistors. Microwave modeling programs were used to ensure proper distribution of the applied current to all of the latching elements. The circuit transferred data at 3 Gigabits per second from one SFQ circuit up to room temperature and back to another SFQ circuit through 3.4 meters of 50-ohm cable.

DOI: 10.1109/77.621785

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Interface circuits for the transfer of data between Single Flux Quantum (SPQ) circuits have been designed, fabricated, and operated at speeds up to 3 Gigabits per second. The circuit employed an improved version of the SFQ/Latch converter, a Modified Variable Threshold Logic (MVTL) OR/AND gate, a 3/spl times/ latching amplifier, and a 3/spl times/-to-10/spl times/ latching amplifier. The amplifier circuits employed stacks of latching junctions. Resistors between the parallel stacks of junctions damped residual currents to prevent flux trapping during reset. Tolerance to critical current variations in the series stacks of junctions was provided by inductive chokes on the input junction shunting resistors. Microwave modeling programs were used to ensure proper distribution of the applied current to all of the latching elements. The circuit transferred data at 3 Gigabits per second from one SFQ circuit up to room temperature and back to another SFQ circuit through 3.4 meters of 50-ohm cable.

Digital circuits have been developed to interface superconductive electronic chips with high speed 50-/spl Omega/ transmission lines. Digital data at 1 Gigabit per second was transferred through a Josephson chip in a first cryostat to another Josephson chip in a second cryostat. The chips were connected by more than 3 meters of 50-/spl Omega/ transmission line. No semiconductor amplifiers were used in this data path. A Hewlett Packard data source provided the original data to the first chip, which converted it to SFQ data. Output interface circuits were driven by a 2-GHz external clock to latch series strings of 10 junctions and drive 2-Gbps data into a 50-/spl Omega/ cable. In the second cryostat, a latching three-junction interferometer with a two-turn control line converted the input signal to latched data and switched an MVTL OR-gate output. This demonstration showed that low-power Josephson digital circuits can be integrated into multichip digital subsystems that can pass data at high rates without the use of power-hungry semiconductor amplifiers.

High-speed logic operation of an output interface circuit for a single-flux-quantum (SFQ) system was demonstrated at a data rate of 5 Gb/s. Using NEC's 2.5-kA/cm/sup 2/ Nb junction process, we designed, fabricated, and tested the interface circuit consisting of a 2-b SFQ demultiplexer and two Josephson latching drivers. We verified the proper operation of the demultiplexer. The interface can convert 5-Gb/s SFQ-pulse data into two-channel 2.5-Gb/s return-to-zero data with an amplitude of approximately 6 mV.

Latching-type driver circuits integrated with high-temperature superconductivity (HTS) junctions and two types of resistor were fabricated. These circuits could successfully perform latching operation by means of a single-flux-quantum (SFQ) signal input. Ramp-edge-type HTS junctions were fabricated by interface engineering and showed a hysteretic current-voltage characteristics under a temperature of 50 K. The critical current (I/sub c/) of these 5-micron-wide junctions was about 0.2 mA and the I/sub c/R/sub n/ product was about 1.7 mV at 4.2 K. The circuits included two types of resistors, which were made of RF-magnetron-sputtered indium-tin-oxide (ITO) and Au films. A driver with a parallel 2-junction-stack could convert an SFQ pulse, which was transformed through several Josephson transmission lines (JTL's) from a DC/SFQ circuit, to a 2.3-mV level signal.

We have designed circuits to transmit and receive bits generated by Single-Flux-Quantum (SFQ) circuits. Our circuits were fabricated using shunted Nb-AlOx-Nb junctions. The transmitter is a series array of dc SQUIDs driven into the voltage state in response to an input SFQ pulse. The receiver circuit is inductively coupled to the transmitter. Current from the transmitter biases a junction race in the receiver such that a clock pulse either passes (a '1' bit) or does not (a '0' bit). We have measured a maximum peak-to-peak amplitude from the transmitter of 296 /spl mu/V at a clock rate of 2.5 GHz, and 187 /spl mu/V at 5 GHz.

The high-speed operation of a one-channel output interface for a single-flux quantum (SFQ) system has been demonstrated. The interface consisted of a Josephson latching driver, a room-temperature semiconductor amplifier, and a decision circuit module. The Josephson latching driver was fabricated by using a 2.5-kA/cm/sup 2/ standard Nb junction process and used to amplify an SFQ pulse into a 5.5-mV level signal at 10 Gb/s. The interface converted the SFQ pulse signal into a nonreturn-to-zero signal having an amplitude of 1 V at 10 Gb/s.